242 lines
7.8 KiB
C
242 lines
7.8 KiB
C
/*
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* Copyright (c) 2006-2019, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2019-02-05 gw first version
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* 2019-05-05 Zero-Free Adding multiple configurations for system clock frequency
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*/
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#include <board.h>
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void SystemClock_Config(void)
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{
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RCC_OscInitTypeDef RCC_OscInitStruct = {0};
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RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
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RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
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#ifdef BSP_USING_ONCHIP_RTC
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/**Configure LSE Drive Capability
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*/
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HAL_PWR_EnableBkUpAccess();
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__HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW);
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#endif
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/**Initializes the CPU, AHB and APB busses clocks
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*/
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RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
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RCC_OscInitStruct.HSIState = RCC_HSI_ON;
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RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
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RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
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RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
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RCC_OscInitStruct.PLL.PLLM = 1;
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RCC_OscInitStruct.PLL.PLLN = 10;
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RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV7;
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RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
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RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
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if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
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{
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Error_Handler();
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}
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/**Initializes the CPU, AHB and APB busses clocks
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*/
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RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
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| RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
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RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
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RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
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RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
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RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
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if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK)
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{
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Error_Handler();
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}
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PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART2;
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PeriphClkInit.Usart2ClockSelection = RCC_USART2CLKSOURCE_PCLK1;
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if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
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{
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Error_Handler();
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}
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/**Configure the main internal regulator output voltage
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*/
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if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1) != HAL_OK)
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{
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Error_Handler();
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}
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}
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#ifdef RT_USING_PM
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void SystemClock_MSI_ON(void)
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{
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RCC_OscInitTypeDef RCC_OscInitStruct = {0};
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RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
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/* Initializes the CPU, AHB and APB busses clocks */
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RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
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RCC_OscInitStruct.MSIState = RCC_MSI_ON;
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if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
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{
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RT_ASSERT(0);
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}
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RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
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RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI;
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if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
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{
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Error_Handler();
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}
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}
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void SystemClock_MSI_OFF(void)
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{
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RCC_OscInitTypeDef RCC_OscInitStruct = {0};
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RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
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RCC_OscInitStruct.HSIState = RCC_MSI_OFF;
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RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; /* No update on PLL */
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if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
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{
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Error_Handler();
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}
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}
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void SystemClock_80M(void)
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{
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RCC_OscInitTypeDef RCC_OscInitStruct;
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RCC_ClkInitTypeDef RCC_ClkInitStruct;
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/**Initializes the CPU, AHB and APB busses clocks */
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RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
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RCC_OscInitStruct.HSIState = RCC_HSI_ON;
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RCC_OscInitStruct.HSICalibrationValue = 16;
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RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
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RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
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RCC_OscInitStruct.PLL.PLLM = 1;
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RCC_OscInitStruct.PLL.PLLN = 10;
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RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV7;
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RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
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RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
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if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
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{
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Error_Handler();
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}
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/**Initializes the CPU, AHB and APB busses clocks
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*/
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RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
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| RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
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RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
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RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
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RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
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RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
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if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK)
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{
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Error_Handler();
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}
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}
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void SystemClock_24M(void)
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{
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RCC_OscInitTypeDef RCC_OscInitStruct;
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RCC_ClkInitTypeDef RCC_ClkInitStruct;
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RCC_PeriphCLKInitTypeDef PeriphClkInit;
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/** Initializes the CPU, AHB and APB busses clocks */
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RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
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RCC_OscInitStruct.HSIState = RCC_HSI_ON;
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RCC_OscInitStruct.HSICalibrationValue = 16;
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RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
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RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
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RCC_OscInitStruct.PLL.PLLM = 1;
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RCC_OscInitStruct.PLL.PLLN = 12;
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RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV7;
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RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
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RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV8;
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if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
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{
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Error_Handler();
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}
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/** Initializes the CPU, AHB and APB busses clocks */
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RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
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| RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
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RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
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RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
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RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
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RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
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if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
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{
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Error_Handler();
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}
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PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART2;
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PeriphClkInit.Usart2ClockSelection = RCC_USART2CLKSOURCE_PCLK1;
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if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
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{
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Error_Handler();
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}
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}
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void SystemClock_2M(void)
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{
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RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
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RCC_OscInitTypeDef RCC_OscInitStruct = {0};
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/* MSI is enabled after System reset, update MSI to 2Mhz (RCC_MSIRANGE_5) */
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RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
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RCC_OscInitStruct.MSIState = RCC_MSI_ON;
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RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_5;
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RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
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RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
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if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
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{
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/* Initialization Error */
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Error_Handler();
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}
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/* Select MSI as system clock source and configure the HCLK, PCLK1 and PCLK2
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clocks dividers */
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RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
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RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI;
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RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
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RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
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RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
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if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK)
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{
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/* Initialization Error */
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Error_Handler();
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}
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}
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/**
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* @brief Configures system clock after wake-up from STOP: enable HSI, PLL
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* and select PLL as system clock source.
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* @param None
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* @retval None
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*/
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void SystemClock_ReConfig(uint8_t mode)
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{
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SystemClock_MSI_ON();
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switch (mode)
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{
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case PM_RUN_MODE_HIGH_SPEED:
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case PM_RUN_MODE_NORMAL_SPEED:
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SystemClock_80M();
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break;
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case PM_RUN_MODE_MEDIUM_SPEED:
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SystemClock_24M();
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break;
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case PM_RUN_MODE_LOW_SPEED:
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SystemClock_2M();
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break;
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default:
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break;
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}
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// SystemClock_MSI_OFF();
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}
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#endif
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