358 lines
9.5 KiB
C
358 lines
9.5 KiB
C
/*
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* Copyright (c) 2006-2024, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2017-08-08 Yang the first version
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* 2019-07-19 yandld The first version for MCXN
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* 2023-02-0 Alex Yang update driver
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*/
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#include <rtdevice.h>
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#include "fsl_usdhc.h"
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#ifdef RT_USING_SDIO
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//#define MMCSD_DEBUG
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#ifdef MMCSD_DEBUG
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#define MMCSD_DGB rt_kprintf
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#else
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#define MMCSD_DGB(fmt, ...)
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#endif
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#define USDHC_ADMA_TABLE_WORDS (32U) /* define the ADMA descriptor table length */
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#define USDHC_ADMA2_ADDR_ALIGN (4U) /* define the ADMA2 descriptor table addr align size */
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AT_NONCACHEABLE_SECTION_ALIGN(uint32_t g_usdhcAdma2Table[USDHC_ADMA_TABLE_WORDS], USDHC_ADMA2_ADDR_ALIGN);
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struct mcx_mmcsd
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{
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struct rt_mmcsd_host *host;
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USDHC_Type *USDHC;
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uint32_t *usdhc_adma2_table;
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};
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#define USDHC_DMA_MODE kUSDHC_DmaModeAdma2
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#define USDHC_ENDIAN_MODE kUSDHC_EndianModeLittle
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#define USDHC_READ_BURST_LEN (8U) /*!< number of words USDHC read in a single burst */
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#define USDHC_WRITE_BURST_LEN (8U) /*!< number of words USDHC write in a single burst */
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#define USDHC_DATA_TIMEOUT (0xFU) /*!< data timeout counter value */
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#define SDMMCHOST_SUPPORT_MAX_BLOCK_LENGTH (4096U)
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#define SDMMCHOST_SUPPORT_MAX_BLOCK_COUNT (USDHC_MAX_BLOCK_COUNT)
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/* Read/write watermark level. The bigger value indicates DMA has higher read/write performance. */
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#define USDHC_READ_WATERMARK_LEVEL (0x80U)
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#define USDHC_WRITE_WATERMARK_LEVEL (0x80U)
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static void SDMMCHOST_ErrorRecovery(USDHC_Type *base)
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{
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uint32_t status = 0U;
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/* get host present status */
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status = USDHC_GetPresentStatusFlags(base);
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/* check command inhibit status flag */
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if ((status & kUSDHC_CommandInhibitFlag) != 0U)
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{
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/* reset command line */
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USDHC_Reset(base, kUSDHC_ResetCommand, 1000U);
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}
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/* check data inhibit status flag */
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if ((status & kUSDHC_DataInhibitFlag) != 0U)
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{
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/* reset data line */
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USDHC_Reset(base, kUSDHC_ResetData, 1000U);
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}
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}
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static void mcx_sdmmc_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req)
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{
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struct mcx_mmcsd *mmcsd;
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struct rt_mmcsd_cmd *cmd;
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struct rt_mmcsd_data *data;
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status_t error;
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usdhc_adma_config_t dmaConfig;
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usdhc_transfer_t fsl_content = {0};
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usdhc_command_t fsl_command = {0};
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usdhc_data_t fsl_data = {0};
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rt_uint32_t *buf = NULL;
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RT_ASSERT(host != RT_NULL);
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RT_ASSERT(req != RT_NULL);
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mmcsd = (struct mcx_mmcsd *)host->private_data;
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RT_ASSERT(mmcsd != RT_NULL);
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cmd = req->cmd;
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RT_ASSERT(cmd != RT_NULL);
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MMCSD_DGB("\tcmd->cmd_code: %02d, cmd->arg: %08x, cmd->flags: %08x --> ", cmd->cmd_code, cmd->arg, cmd->flags);
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data = cmd->data;
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rt_memset(&dmaConfig, 0, sizeof(usdhc_adma_config_t));
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/* config adma */
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dmaConfig.dmaMode = USDHC_DMA_MODE;
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dmaConfig.burstLen = kUSDHC_EnBurstLenForINCR;
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dmaConfig.admaTable = mmcsd->usdhc_adma2_table;
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dmaConfig.admaTableWords = USDHC_ADMA_TABLE_WORDS;
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fsl_command.index = cmd->cmd_code;
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fsl_command.argument = cmd->arg;
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if (cmd->cmd_code == STOP_TRANSMISSION)
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fsl_command.type = kCARD_CommandTypeAbort;
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else
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fsl_command.type = kCARD_CommandTypeNormal;
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switch (cmd->flags & RESP_MASK)
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{
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case RESP_NONE:
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fsl_command.responseType = kCARD_ResponseTypeNone;
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break;
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case RESP_R1:
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fsl_command.responseType = kCARD_ResponseTypeR1;
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break;
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case RESP_R1B:
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fsl_command.responseType = kCARD_ResponseTypeR1b;
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break;
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case RESP_R2:
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fsl_command.responseType = kCARD_ResponseTypeR2;
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break;
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case RESP_R3:
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fsl_command.responseType = kCARD_ResponseTypeR3;
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break;
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case RESP_R4:
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fsl_command.responseType = kCARD_ResponseTypeR4;
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break;
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case RESP_R6:
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fsl_command.responseType = kCARD_ResponseTypeR6;
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break;
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case RESP_R7:
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fsl_command.responseType = kCARD_ResponseTypeR7;
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break;
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case RESP_R5:
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fsl_command.responseType = kCARD_ResponseTypeR5;
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break;
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default:
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RT_ASSERT(NULL);
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}
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fsl_command.flags = 0;
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fsl_content.command = &fsl_command;
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if (data)
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{
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if (req->stop != NULL)
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fsl_data.enableAutoCommand12 = true;
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else
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fsl_data.enableAutoCommand12 = false;
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fsl_data.enableAutoCommand23 = false;
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fsl_data.enableIgnoreError = false;
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fsl_data.dataType = kUSDHC_TransferDataNormal; //todo : update data type
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fsl_data.blockSize = data->blksize;
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fsl_data.blockCount = data->blks;
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MMCSD_DGB(" blksize:%d, blks:%d ", fsl_data.blockSize, fsl_data.blockCount);
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if ((cmd->cmd_code == WRITE_BLOCK) || (cmd->cmd_code == WRITE_MULTIPLE_BLOCK))
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{
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if (buf)
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{
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MMCSD_DGB(" write(data->buf to buf) ");
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rt_memcpy(buf, data->buf, fsl_data.blockSize * fsl_data.blockCount);
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fsl_data.txData = (uint32_t const *)buf;
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}
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else
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{
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fsl_data.txData = (uint32_t const *)data->buf;
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}
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fsl_data.rxData = NULL;
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}
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else
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{
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if (buf)
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{
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fsl_data.rxData = (uint32_t *)buf;
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}
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else
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{
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fsl_data.rxData = (uint32_t *)data->buf;
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}
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fsl_data.txData = NULL;
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}
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fsl_content.data = &fsl_data;
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}
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else
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{
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fsl_content.data = NULL;
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}
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error = USDHC_TransferBlocking(mmcsd->USDHC, &dmaConfig, &fsl_content);
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if (error != kStatus_Success)
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{
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SDMMCHOST_ErrorRecovery(mmcsd->USDHC);
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MMCSD_DGB(" ***USDHC_TransferBlocking error: %d*** --> \n", error);
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cmd->err = -RT_ERROR;
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}
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if (buf)
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{
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if (fsl_data.rxData)
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{
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MMCSD_DGB("read copy buf to data->buf ");
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rt_memcpy(data->buf, buf, fsl_data.blockSize * fsl_data.blockCount);
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}
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rt_free_align(buf);
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}
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if ((cmd->flags & RESP_MASK) == RESP_R2)
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{
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cmd->resp[3] = fsl_command.response[0];
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cmd->resp[2] = fsl_command.response[1];
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cmd->resp[1] = fsl_command.response[2];
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cmd->resp[0] = fsl_command.response[3];
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MMCSD_DGB(" resp 0x%08X 0x%08X 0x%08X 0x%08X\n",
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cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3]);
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}
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else
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{
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cmd->resp[0] = fsl_command.response[0];
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MMCSD_DGB(" resp 0x%08X\n", cmd->resp[0]);
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}
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mmcsd_req_complete(host);
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return;
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}
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static void mcx_sdmmc_set_iocfg(struct rt_mmcsd_host *host, struct rt_mmcsd_io_cfg *io_cfg)
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{
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MMCSD_DGB("%s\r\n", __FUNCTION__);
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struct mcx_mmcsd *mmcsd;
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mmcsd = (struct mcx_mmcsd *) host->private_data;
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uint32_t sdxc_clock = io_cfg->clock;
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MMCSD_DGB("sdxc_clock:%d\r\n", sdxc_clock);
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MMCSD_DGB("bus_width:%d\r\n", io_cfg->bus_width);
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if (sdxc_clock != 0U)
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{
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USDHC_SetSdClock(mmcsd->USDHC, CLOCK_GetUsdhcClkFreq(), sdxc_clock);
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switch (io_cfg->bus_width)
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{
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case MMCSD_BUS_WIDTH_4:
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USDHC_SetDataBusWidth(mmcsd->USDHC, kUSDHC_DataBusWidth4Bit);
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break;
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case MMCSD_BUS_WIDTH_8:
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USDHC_SetDataBusWidth(mmcsd->USDHC, kUSDHC_DataBusWidth4Bit);
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break;
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default:
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USDHC_SetDataBusWidth(mmcsd->USDHC, kUSDHC_DataBusWidth1Bit);
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break;
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}
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}
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rt_thread_mdelay(20);
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}
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static const struct rt_mmcsd_host_ops mcx_mmcsd_host_ops =
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{
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.request = mcx_sdmmc_request,
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.set_iocfg = mcx_sdmmc_set_iocfg,
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.get_card_status = NULL,
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.enable_sdio_irq = NULL, // Do not use the interrupt mode, use DMA instead
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};
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int rt_hw_sdio_init(void)
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{
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struct rt_mmcsd_host *host = RT_NULL;
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struct mcx_mmcsd *mmcsd = RT_NULL;
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host = mmcsd_alloc_host();
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if (!host)
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{
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return -RT_ERROR;
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}
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mmcsd = rt_malloc(sizeof(struct mcx_mmcsd));
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if (!mmcsd)
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{
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MMCSD_DGB("alloc mci failed\n");
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goto err;
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}
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rt_memset(mmcsd, 0, sizeof(struct mcx_mmcsd));
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mmcsd->USDHC = USDHC0;
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mmcsd->usdhc_adma2_table = g_usdhcAdma2Table;
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host->ops = &mcx_mmcsd_host_ops;
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host->freq_min = 375000;
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host->freq_max = 50000000;
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host->valid_ocr = VDD_32_33 | VDD_33_34;
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host->flags = MMCSD_MUTBLKWRITE | MMCSD_BUSWIDTH_4 | MMCSD_SUP_HIGHSPEED | MMCSD_SUP_SDIO_IRQ;
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host->max_seg_size = 65535;
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host->max_dma_segs = 2;
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host->max_blk_size = SDMMCHOST_SUPPORT_MAX_BLOCK_LENGTH;
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host->max_blk_count = SDMMCHOST_SUPPORT_MAX_BLOCK_COUNT;
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mmcsd->host = host;
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/* attach FRO HF to USDHC */
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CLOCK_SetClkDiv(kCLOCK_DivUSdhcClk, 1u);
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CLOCK_AttachClk(kFRO_HF_to_USDHC);
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MMCSD_DGB("SDIO clock:%dHz\r\n", CLOCK_GetUsdhcClkFreq());
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/* Initializes SDHC. */
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usdhc_config_t config;
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config.dataTimeout = USDHC_DATA_TIMEOUT;
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config.endianMode = USDHC_ENDIAN_MODE;
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config.readWatermarkLevel = USDHC_READ_WATERMARK_LEVEL;
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config.writeWatermarkLevel = USDHC_WRITE_WATERMARK_LEVEL;
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config.readBurstLen = USDHC_READ_BURST_LEN;
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config.writeBurstLen = USDHC_WRITE_BURST_LEN;
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USDHC_Init(USDHC0, &config);
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host->private_data = mmcsd;
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mmcsd_change(host);
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return 0;
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err:
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mmcsd_free_host(host);
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return -RT_ENOMEM;
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}
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INIT_DEVICE_EXPORT(rt_hw_sdio_init);
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#endif /* endif RT_USING_SDIO */
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