299 lines
7.8 KiB
C
299 lines
7.8 KiB
C
/*******************************************************************************
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* (c) Copyright 2008-2015 Microsemi SoC Products Group. All rights reserved.
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*
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* SmartFusion2 microcontroller subsystem GPIO bare metal driver implementation.
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*
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* SVN $Revision: 7749 $
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* SVN $Date: 2015-09-04 14:32:09 +0530 (Fri, 04 Sep 2015) $
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*/
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#include "mss_gpio.h"
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#include "../../CMSIS/mss_assert.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/*-------------------------------------------------------------------------*//**
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* Defines.
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*/
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#define GPIO_INT_ENABLE_MASK ((uint32_t)0x00000008uL)
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#define OUTPUT_BUFFER_ENABLE_MASK 0x00000004u
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#define NB_OF_GPIO ((uint32_t)32)
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/*-------------------------------------------------------------------------*//**
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* Lookup table of GPIO configuration registers address indexed on GPIO ID.
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*/
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static uint32_t volatile * const g_config_reg_lut[NB_OF_GPIO] =
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{
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&(GPIO->GPIO_0_CFG),
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&(GPIO->GPIO_1_CFG),
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&(GPIO->GPIO_2_CFG),
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&(GPIO->GPIO_3_CFG),
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&(GPIO->GPIO_4_CFG),
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&(GPIO->GPIO_5_CFG),
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&(GPIO->GPIO_6_CFG),
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&(GPIO->GPIO_7_CFG),
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&(GPIO->GPIO_8_CFG),
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&(GPIO->GPIO_9_CFG),
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&(GPIO->GPIO_10_CFG),
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&(GPIO->GPIO_11_CFG),
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&(GPIO->GPIO_12_CFG),
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&(GPIO->GPIO_13_CFG),
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&(GPIO->GPIO_14_CFG),
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&(GPIO->GPIO_15_CFG),
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&(GPIO->GPIO_16_CFG),
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&(GPIO->GPIO_17_CFG),
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&(GPIO->GPIO_18_CFG),
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&(GPIO->GPIO_19_CFG),
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&(GPIO->GPIO_20_CFG),
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&(GPIO->GPIO_21_CFG),
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&(GPIO->GPIO_22_CFG),
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&(GPIO->GPIO_23_CFG),
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&(GPIO->GPIO_24_CFG),
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&(GPIO->GPIO_25_CFG),
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&(GPIO->GPIO_26_CFG),
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&(GPIO->GPIO_27_CFG),
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&(GPIO->GPIO_28_CFG),
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&(GPIO->GPIO_29_CFG),
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&(GPIO->GPIO_30_CFG),
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&(GPIO->GPIO_31_CFG)
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};
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/*-------------------------------------------------------------------------*//**
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* Lookup table of Cortex-M3 GPIO interrupt number indexed on GPIO ID.
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*/
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static const IRQn_Type g_gpio_irqn_lut[NB_OF_GPIO] =
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{
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GPIO0_IRQn,
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GPIO1_IRQn,
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GPIO2_IRQn,
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GPIO3_IRQn,
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GPIO4_IRQn,
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GPIO5_IRQn,
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GPIO6_IRQn,
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GPIO7_IRQn,
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GPIO8_IRQn,
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GPIO9_IRQn,
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GPIO10_IRQn,
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GPIO11_IRQn,
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GPIO12_IRQn,
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GPIO13_IRQn,
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GPIO14_IRQn,
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GPIO15_IRQn,
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GPIO16_IRQn,
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GPIO17_IRQn,
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GPIO18_IRQn,
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GPIO19_IRQn,
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GPIO20_IRQn,
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GPIO21_IRQn,
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GPIO22_IRQn,
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GPIO23_IRQn,
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GPIO24_IRQn,
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GPIO25_IRQn,
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GPIO26_IRQn,
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GPIO27_IRQn,
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GPIO28_IRQn,
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GPIO29_IRQn,
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GPIO30_IRQn,
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GPIO31_IRQn
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};
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/*-------------------------------------------------------------------------*//**
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* MSS_GPIO_init
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* See "mss_gpio.h" for details of how to use this function.
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*/
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void MSS_GPIO_init( void )
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{
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uint32_t inc;
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/* reset MSS GPIO hardware */
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SYSREG->SOFT_RST_CR |= SYSREG_GPIO_SOFTRESET_MASK;
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SYSREG->SOFT_RST_CR |= (SYSREG_GPIO_7_0_SOFTRESET_MASK |
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SYSREG_GPIO_15_8_SOFTRESET_MASK |
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SYSREG_GPIO_23_16_SOFTRESET_MASK |
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SYSREG_GPIO_31_24_SOFTRESET_MASK);
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/* Clear any previously pended MSS GPIO interrupt */
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for(inc = 0U; inc < NB_OF_GPIO; ++inc)
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{
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NVIC_DisableIRQ(g_gpio_irqn_lut[inc]);
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NVIC_ClearPendingIRQ(g_gpio_irqn_lut[inc]);
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}
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/* Take MSS GPIO hardware out of reset. */
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SYSREG->SOFT_RST_CR &= ~(SYSREG_GPIO_7_0_SOFTRESET_MASK |
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SYSREG_GPIO_15_8_SOFTRESET_MASK |
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SYSREG_GPIO_23_16_SOFTRESET_MASK |
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SYSREG_GPIO_31_24_SOFTRESET_MASK);
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SYSREG->SOFT_RST_CR &= ~SYSREG_GPIO_SOFTRESET_MASK;
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}
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/*-------------------------------------------------------------------------*//**
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* MSS_GPIO_config
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* See "mss_gpio.h" for details of how to use this function.
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*/
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void MSS_GPIO_config
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(
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mss_gpio_id_t port_id,
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uint32_t config
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)
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{
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uint32_t gpio_idx = (uint32_t)port_id;
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ASSERT(gpio_idx < NB_OF_GPIO);
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if(gpio_idx < NB_OF_GPIO)
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{
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*(g_config_reg_lut[gpio_idx]) = config;
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}
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}
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/*-------------------------------------------------------------------------*//**
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* MSS_GPIO_set_output
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* See "mss_gpio.h" for details of how to use this function.
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*/
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void MSS_GPIO_set_output
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(
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mss_gpio_id_t port_id,
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uint8_t value
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)
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{
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uint32_t gpio_setting;
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uint32_t gpio_idx = (uint32_t)port_id;
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ASSERT(gpio_idx < NB_OF_GPIO);
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if(gpio_idx < NB_OF_GPIO)
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{
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gpio_setting = GPIO->GPIO_OUT;
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gpio_setting &= ~((uint32_t)0x01u << gpio_idx);
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gpio_setting |= ((uint32_t)value & 0x01u) << gpio_idx;
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GPIO->GPIO_OUT = gpio_setting;
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}
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}
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/*-------------------------------------------------------------------------*//**
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* MSS_GPIO_drive_inout
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* See "mss_gpio.h" for details of how to use this function.
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*/
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void MSS_GPIO_drive_inout
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(
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mss_gpio_id_t port_id,
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mss_gpio_inout_state_t inout_state
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)
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{
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uint32_t outputs_state;
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uint32_t config;
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uint32_t gpio_idx = (uint32_t)port_id;
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ASSERT(gpio_idx < NB_OF_GPIO);
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if(gpio_idx < NB_OF_GPIO)
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{
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switch(inout_state)
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{
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case MSS_GPIO_DRIVE_HIGH:
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/* Set output high */
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outputs_state = GPIO->GPIO_OUT;
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outputs_state |= (uint32_t)1 << gpio_idx;
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GPIO->GPIO_OUT = outputs_state;
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/* Enable output buffer */
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config = *(g_config_reg_lut[gpio_idx]);
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config |= OUTPUT_BUFFER_ENABLE_MASK;
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*(g_config_reg_lut[gpio_idx]) = config;
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break;
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case MSS_GPIO_DRIVE_LOW:
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/* Set output low */
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outputs_state = GPIO->GPIO_OUT;
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outputs_state &= ~((uint32_t)((uint32_t)1 << gpio_idx));
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GPIO->GPIO_OUT = outputs_state;
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/* Enable output buffer */
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config = *(g_config_reg_lut[gpio_idx]);
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config |= OUTPUT_BUFFER_ENABLE_MASK;
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*(g_config_reg_lut[gpio_idx]) = config;
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break;
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case MSS_GPIO_HIGH_Z:
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/* Disable output buffer */
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config = *(g_config_reg_lut[gpio_idx]);
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config &= ~OUTPUT_BUFFER_ENABLE_MASK;
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*(g_config_reg_lut[gpio_idx]) = config;
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break;
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default:
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ASSERT(0);
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break;
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}
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}
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}
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/*-------------------------------------------------------------------------*//**
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* MSS_GPIO_enable_irq
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* See "mss_gpio.h" for details of how to use this function.
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*/
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void MSS_GPIO_enable_irq
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(
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mss_gpio_id_t port_id
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)
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{
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uint32_t cfg_value;
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uint32_t gpio_idx = (uint32_t)port_id;
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ASSERT(gpio_idx < NB_OF_GPIO);
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if(gpio_idx < NB_OF_GPIO)
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{
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cfg_value = *(g_config_reg_lut[gpio_idx]);
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*(g_config_reg_lut[gpio_idx]) = (cfg_value | GPIO_INT_ENABLE_MASK);
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NVIC_EnableIRQ(g_gpio_irqn_lut[gpio_idx]);
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}
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}
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/*-------------------------------------------------------------------------*//**
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* MSS_GPIO_disable_irq
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* See "mss_gpio.h" for details of how to use this function.
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*/
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void MSS_GPIO_disable_irq
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(
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mss_gpio_id_t port_id
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)
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{
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uint32_t cfg_value;
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uint32_t gpio_idx = (uint32_t)port_id;
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ASSERT(gpio_idx < NB_OF_GPIO);
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if(gpio_idx < NB_OF_GPIO)
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{
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cfg_value = *(g_config_reg_lut[gpio_idx]);
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*(g_config_reg_lut[gpio_idx]) = (cfg_value & ~GPIO_INT_ENABLE_MASK);
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}
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}
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/*-------------------------------------------------------------------------*//**
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* MSS_GPIO_clear_irq
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* See "mss_gpio.h" for details of how to use this function.
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*/
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void MSS_GPIO_clear_irq
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(
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mss_gpio_id_t port_id
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)
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{
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uint32_t gpio_idx = (uint32_t)port_id;
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ASSERT(gpio_idx < NB_OF_GPIO);
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if(gpio_idx < NB_OF_GPIO)
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{
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GPIO->GPIO_IRQ = ((uint32_t)1) << gpio_idx;
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}
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__ASM volatile ("dsb");
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}
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#ifdef __cplusplus
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}
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#endif
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