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9ef986929c
Previously Loongson 1B and Loongson 1C have their own libcpu implemention, but they're almost identical. So we merge them into gs232 and adapt to new common code. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
78 lines
1.7 KiB
C
78 lines
1.7 KiB
C
/*
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* Copyright (c) 2006-2019, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2010-05-27 swkyer first version
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*/
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#include <rtthread.h>
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#include <mips.h>
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mips32_core_cfg_t g_mips_core =
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{
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16, /* icache_line_size */
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256, /* icache_lines_per_way */
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4, /* icache_ways */
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16, /* dcache_line_size */
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256, /* dcache_lines_per_way */
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4, /* dcache_ways */
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16, /* max_tlb_entries */
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};
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static rt_uint16_t m_pow(rt_uint16_t b, rt_uint16_t n)
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{
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rt_uint16_t rets = 1;
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while (n--)
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rets *= b;
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return rets;
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}
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static rt_uint16_t m_log2(rt_uint16_t b)
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{
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rt_uint16_t rets = 0;
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while (b != 1)
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{
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b /= 2;
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rets++;
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}
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return rets;
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}
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/**
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* read core attribute
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*/
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void mips32_cfg_init(void)
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{
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rt_uint16_t val;
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rt_uint32_t cp0_config1;
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cp0_config1 = read_c0_config();
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if (cp0_config1 & 0x80000000)
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{
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cp0_config1 = read_c0_config1();
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val = (cp0_config1 & (7<<22))>>22;
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g_mips_core.icache_lines_per_way = 64 * m_pow(2, val);
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val = (cp0_config1 & (7<<19))>>19;
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g_mips_core.icache_line_size = 2 * m_pow(2, val);
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val = (cp0_config1 & (7<<16))>>16;
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g_mips_core.icache_ways = val + 1;
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val = (cp0_config1 & (7<<13))>>13;
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g_mips_core.dcache_lines_per_way = 64 * m_pow(2, val);
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val = (cp0_config1 & (7<<10))>>10;
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g_mips_core.dcache_line_size = 2 * m_pow(2, val);
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val = (cp0_config1 & (7<<7))>>7;
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g_mips_core.dcache_ways = val + 1;
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val = (cp0_config1 & (0x3F<<25))>>25;
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g_mips_core.max_tlb_entries = val + 1;
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}
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}
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