342 lines
8.3 KiB
C
342 lines
8.3 KiB
C
/*
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* Copyright (c) 2006-2024 RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2022-11-22 GuEe-GUI first version
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*/
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/*
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* The Synopsys DesignWare 8250 has an extra feature whereby it detects if the
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* LCR is written whilst busy. If it is, then a busy detect interrupt is
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* raised, the LCR needs to be rewritten and the uart status register read.
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*/
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#include <rtthread.h>
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#include "8250.h"
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/* Offsets for the DesignWare specific registers */
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#define DW_UART_USR 0x1f /* UART Status Register */
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#define DW_UART_DMASA 0xa8 /* DMA Software Ack */
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#define OCTEON_UART_USR 0x27 /* UART Status Register */
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#define RZN1_UART_TDMACR 0x10c /* DMA Control Register Transmit Mode */
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#define RZN1_UART_RDMACR 0x110 /* DMA Control Register Receive Mode */
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/* DesignWare specific register fields */
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#define DW_UART_MCR_SIRE RT_BIT(6)
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/* Renesas specific register fields */
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#define RZN1_UART_xDMACR_DMA_EN RT_BIT(0)
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#define RZN1_UART_xDMACR_1_WORD_BURST (0 << 1)
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#define RZN1_UART_xDMACR_4_WORD_BURST (1 << 1)
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#define RZN1_UART_xDMACR_8_WORD_BURST (2 << 1)
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#define RZN1_UART_xDMACR_BLK_SZ(x) ((x) << 3)
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/* Quirks */
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#define DW_UART_QUIRK_OCTEON RT_BIT(0)
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#define DW_UART_QUIRK_ARMADA_38X RT_BIT(1)
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#define DW_UART_QUIRK_SKIP_SET_RATE RT_BIT(2)
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#define DW_UART_QUIRK_IS_DMA_FC RT_BIT(3)
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struct dw8250_platform_data
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{
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rt_uint8_t usr_reg;
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rt_uint32_t cpr_val;
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rt_uint32_t quirks;
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};
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struct dw8250
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{
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struct serial8250 parent;
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struct rt_spinlock spinlock;
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struct rt_clk *pclk;
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rt_bool_t uart_16550_compatible;
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struct dw8250_platform_data *platform_data;
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};
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#define to_dw8250(serial8250) rt_container_of(serial8250, struct dw8250, parent)
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static void dw8250_check_lcr(struct serial8250 *serial, int value)
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{
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void *offset = (void *)(serial->base + (UART_LCR << serial->regshift));
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int tries = 1000;
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/* Make sure LCR write wasn't ignored */
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while (tries--)
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{
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rt_uint32_t lcr = serial->serial_in(serial, UART_LCR);
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if ((value & ~UART_LCR_SPAR) == (lcr & ~UART_LCR_SPAR))
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{
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break;
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}
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serial->serial_out(serial, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
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serial->serial_in(serial, UART_RX);
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if (serial->iotype == PORT_MMIO32)
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{
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HWREG32(offset) = value;
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}
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else if (serial->iotype == PORT_MMIO32BE)
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{
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HWREG32(offset) = rt_cpu_to_be32(value);
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}
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else
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{
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HWREG8(offset) = value;
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}
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}
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}
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static void dw8250_serial_out32(struct serial8250 *serial, int offset, int value)
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{
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struct dw8250 *dw8250 = to_dw8250(serial);
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HWREG32(serial->base + (offset << serial->regshift)) = value;
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if (offset == UART_LCR && !dw8250->uart_16550_compatible)
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{
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dw8250_check_lcr(serial, value);
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}
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}
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static rt_uint32_t dw8250_serial_in32(struct serial8250 *serial, int offset)
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{
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return HWREG32(serial->base + (offset << serial->regshift));
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}
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static rt_err_t dw8250_isr(struct serial8250 *serial, int irq)
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{
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unsigned int iir, status;
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struct dw8250 *dw8250 = to_dw8250(serial);
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iir = serial8250_in(serial, UART_IIR);
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/*
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* If don't do this in non-DMA mode then the "RX TIMEOUT" interrupt will
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* fire forever.
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*/
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if ((iir & 0x3f) == UART_IIR_RX_TIMEOUT)
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{
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rt_base_t level = rt_spin_lock_irqsave(&dw8250->spinlock);
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status = serial8250_in(serial, UART_LSR);
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if (!(status & (UART_LSR_DR | UART_LSR_BI)))
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{
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serial8250_in(serial, UART_RX);
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}
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rt_spin_unlock_irqrestore(&dw8250->spinlock, level);
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}
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if (!(iir & UART_IIR_NO_INT))
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{
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rt_hw_serial_isr(&serial->parent, RT_SERIAL_EVENT_RX_IND);
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}
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if ((iir & UART_IIR_BUSY) == UART_IIR_BUSY)
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{
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/* Clear the USR */
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serial8250_in(serial, dw8250->platform_data->usr_reg);
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}
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return RT_EOK;
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}
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static void dw8250_free_resource(struct dw8250 *dw8250)
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{
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struct serial8250 *serial = &dw8250->parent;
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if (serial->base)
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{
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rt_iounmap(serial->base);
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}
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if (serial->clk)
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{
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rt_clk_disable_unprepare(serial->clk);
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rt_clk_put(serial->clk);
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}
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if (dw8250->pclk)
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{
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rt_clk_disable_unprepare(dw8250->pclk);
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rt_clk_put(dw8250->pclk);
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}
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rt_free(dw8250);
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}
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static void dw8250_remove(struct serial8250 *serial)
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{
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struct dw8250 *dw8250 = to_dw8250(serial);
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dw8250_free_resource(dw8250);
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}
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static rt_err_t dw8250_probe(struct rt_platform_device *pdev)
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{
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rt_err_t err;
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rt_uint32_t val;
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struct serial8250 *serial;
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struct rt_device *dev = &pdev->parent;
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struct dw8250 *dw8250 = serial8250_alloc(dw8250);
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struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
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if (!dw8250)
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{
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return -RT_ENOMEM;
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}
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serial = &dw8250->parent;
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serial->base = rt_dm_dev_iomap(dev, 0);
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if (!serial->base)
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{
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err = -RT_EIO;
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goto _free_res;
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}
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serial->irq = rt_dm_dev_get_irq(dev, 0);
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if (serial->irq < 0)
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{
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err = serial->irq;
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goto _free_res;
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}
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serial->clk = rt_clk_get_by_name(dev, "baudclk");
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dw8250->pclk = rt_clk_get_by_name(dev, "apb_pclk");
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if (!serial->clk)
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{
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if ((err = rt_dm_dev_prop_read_u32(dev, "clock-frequency", &serial->freq)))
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{
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goto _free_res;
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}
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}
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else
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{
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if ((err = rt_clk_prepare_enable(serial->clk)))
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{
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goto _free_res;
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}
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serial->freq = rt_clk_get_rate(serial->clk);
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}
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if (!dw8250->pclk)
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{
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err = -RT_EIO;
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goto _free_res;
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}
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if ((err = rt_clk_prepare_enable(dw8250->pclk)))
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{
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goto _free_res;
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}
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rt_dm_dev_prop_read_u32(dev, "reg-shift", &serial->regshift);
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if (!rt_dm_dev_prop_read_u32(dev, "reg-io-width", &val) && val == 4)
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{
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serial->iotype = PORT_MMIO32;
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serial->serial_in = &dw8250_serial_in32;
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serial->serial_out = &dw8250_serial_out32;
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}
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dw8250->uart_16550_compatible = rt_dm_dev_prop_read_bool(dev, "snps,uart-16550-compatible");
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dw8250->platform_data = (struct dw8250_platform_data *)pdev->id->data;
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rt_dm_dev_bind_fwdata(&serial->parent.parent, pdev->parent.ofw_node, &serial->parent);
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serial = &dw8250->parent;
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serial->parent.ops = &serial8250_uart_ops;
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serial->parent.config = config;
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serial->handle_irq = &dw8250_isr;
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serial->remove = &dw8250_remove;
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serial->data = dw8250;
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rt_spin_lock_init(&dw8250->spinlock);
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if ((err = serial8250_setup(serial)))
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{
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goto _free_res;
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}
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return RT_EOK;
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_free_res:
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dw8250_free_resource(dw8250);
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return err;
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}
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static const struct dw8250_platform_data dw8250_dw_apb =
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{
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.usr_reg = DW_UART_USR,
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};
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static const struct dw8250_platform_data dw8250_octeon_3860_data =
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{
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.usr_reg = OCTEON_UART_USR,
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.quirks = DW_UART_QUIRK_OCTEON,
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};
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static const struct dw8250_platform_data dw8250_armada_38x_data =
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{
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.usr_reg = DW_UART_USR,
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.quirks = DW_UART_QUIRK_ARMADA_38X,
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};
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static const struct dw8250_platform_data dw8250_renesas_rzn1_data =
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{
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.usr_reg = DW_UART_USR,
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.cpr_val = 0x00012f32,
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.quirks = DW_UART_QUIRK_IS_DMA_FC,
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};
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static const struct dw8250_platform_data dw8250_starfive_jh7100_data =
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{
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.usr_reg = DW_UART_USR,
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.quirks = DW_UART_QUIRK_SKIP_SET_RATE,
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};
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static const struct rt_ofw_node_id dw8250_ofw_ids[] =
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{
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{ .type = "ttyS", .compatible = "snps,dw-apb-uart", .data = &dw8250_dw_apb },
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{ .type = "ttyS", .compatible = "cavium,octeon-3860-uart", .data = &dw8250_octeon_3860_data },
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{ .type = "ttyS", .compatible = "marvell,armada-38x-uart", .data = &dw8250_armada_38x_data },
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{ .type = "ttyS", .compatible = "renesas,rzn1-uart", .data = &dw8250_renesas_rzn1_data },
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{ .type = "ttyS", .compatible = "starfive,jh7100-uart", .data = &dw8250_starfive_jh7100_data },
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{ /* sentinel */ }
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};
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static struct rt_platform_driver dw8250_driver =
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{
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.name = "dw-apb-uart",
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.ids = dw8250_ofw_ids,
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.probe = dw8250_probe,
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};
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static int dw8250_drv_register(void)
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{
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rt_platform_driver_register(&dw8250_driver);
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return 0;
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}
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INIT_DRIVER_EARLY_EXPORT(dw8250_drv_register);
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