49 lines
1.0 KiB
ArmAsm
49 lines
1.0 KiB
ArmAsm
/*
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* Copyright (c) 2006-2019, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2016-09-19 Urey first version
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*/
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#ifndef __ASSEMBLY__
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#define __ASSEMBLY__
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#endif
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#include "../common/mips.h"
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.text
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.set noreorder
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.globl cache_init
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.ent cache_init
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cache_init:
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.set noreorder
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mtc0 zero, CP0_TAGLO
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move t0, a0 // cache total size
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move t1, a1 // cache line size
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li t2, 0x80000000
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addu t3, t0, t2
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_cache_init_loop:
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cache 8, 0(t2) // icache_index_store_tag
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cache 9, 0(t2) // dcache_index_store_tag
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addu t2, t1
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bne t2, t3, _cache_init_loop
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nop
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mfc0 t0, CP0_CONFIG
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li t1, 0x7
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not t1
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and t0, t0, t1
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or t0, 0x3 // cacheable, noncoherent, write-back, write allocate
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mtc0 t0, CP0_CONFIG
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jr ra
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nop
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.set reorder
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.end cache_init
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