451 lines
8.8 KiB
C
451 lines
8.8 KiB
C
/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2021-08-20 breo.com first version
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*/
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#include <board.h>
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#include "drv_hwtimer.h"
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#define DRV_DEBUG
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#define LOG_TAG "drv.hwtimer"
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#include <drv_log.h>
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#ifdef BSP_USING_HWTIMER
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enum
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{
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#ifdef BSP_USING_HWTIM1
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TIM1_INDEX,
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#endif
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#ifdef BSP_USING_HWTIM2
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TIM2_INDEX,
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#endif
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#ifdef BSP_USING_HWTIM3
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TIM3_INDEX,
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#endif
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#ifdef BSP_USING_HWTIM4
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TIM4_INDEX,
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#endif
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#ifdef BSP_USING_HWTIM5
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TIM5_INDEX,
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#endif
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#ifdef BSP_USING_HWTIM6
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TIM6_INDEX,
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#endif
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#ifdef BSP_USING_HWTIM7
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TIM7_INDEX,
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#endif
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#ifdef BSP_USING_HW_TIM8
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TIM8_INDEX,
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#endif
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#ifdef BSP_USING_HWTIM9
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TIM9_INDEX,
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#endif
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#ifdef BSP_USING_HWTIM10
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TIM10_INDEX,
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#endif
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#ifdef BSP_USING_HWTIM11
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TIM11_INDEX,
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#endif
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#ifdef BSP_USING_HWTIM12
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TIM12_INDEX,
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#endif
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#ifdef BSP_USING_HWTIM13
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TIM13_INDEX,
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#endif
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#ifdef BSP_USING_HWTIM14
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TIM14_INDEX,
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#endif
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#ifdef BSP_USING_HWTIM15
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TIM15_INDEX,
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#endif
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};
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struct n32_hwtimer
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{
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rt_hwtimer_t time_device;
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TIM_Module *tim_handle;
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IRQn_Type tim_irqn;
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char *name;
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};
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static struct n32_hwtimer n32_hwtimer_obj[] =
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{
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#ifdef BSP_USING_HWTIM1
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TIM1_CONFIG,
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#endif
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#ifdef BSP_USING_HWTIM2
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TIM2_CONFIG,
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#endif
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#ifdef BSP_USING_HWTIM3
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TIM3_CONFIG,
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#endif
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#ifdef BSP_USING_HWTIM4
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TIM4_CONFIG,
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#endif
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#ifdef BSP_USING_HWTIM5
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TIM5_CONFIG,
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#endif
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#ifdef BSP_USING_HWTIM6
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TIM6_CONFIG,
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#endif
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#ifdef BSP_USING_HWTIM7
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TIM7_CONFIG,
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#endif
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#ifdef BSP_USING_HWTIM8
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TIM8_CONFIG,
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#endif
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#ifdef BSP_USING_HWTIM9
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TIM9_CONFIG,
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#endif
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#ifdef BSP_USING_HWTIM10
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TIM10_CONFIG,
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#endif
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#ifdef BSP_USING_HWTIM11
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TIM11_CONFIG,
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#endif
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#ifdef BSP_USING_HWTIM12
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TIM12_CONFIG,
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#endif
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#ifdef BSP_USING_HWTIM13
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TIM13_CONFIG,
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#endif
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#ifdef BSP_USING_HWTIM14
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TIM14_CONFIG,
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#endif
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#ifdef BSP_USING_HWTIM15
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TIM15_CONFIG,
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#endif
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};
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static void n32_timer_init(struct rt_hwtimer_device *timer, rt_uint32_t state)
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{
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RCC_ClocksType RCC_ClockStruct;
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TIM_TimeBaseInitType TIM_TimeBaseStructure;
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NVIC_InitType NVIC_InitStructure;
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uint32_t prescaler_value = 0;
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TIM_Module *tim = RT_NULL;
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struct n32_hwtimer *tim_device = RT_NULL;
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RT_ASSERT(timer != RT_NULL);
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if (state)
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{
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tim = (TIM_Module *)timer->parent.user_data;
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tim_device = (struct n32_hwtimer *)timer;
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/* timer clock enable */
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n32_msp_hwtim_init(tim);
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/* timer init */
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RCC_GetClocksFreqValue(&RCC_ClockStruct);
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/* Set timer clock is 1Mhz */
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prescaler_value = (uint32_t)(RCC_ClockStruct.SysclkFreq / 10000) - 1;
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TIM_TimeBaseStructure.Period = 10000 - 1;
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rt_kprintf("Period=[%d]", TIM_TimeBaseStructure.Period);
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TIM_TimeBaseStructure.Prescaler = prescaler_value;
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rt_kprintf("Prescaler=[%d]", TIM_TimeBaseStructure.Prescaler);
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TIM_TimeBaseStructure.ClkDiv = TIM_CLK_DIV1;
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TIM_TimeBaseStructure.RepetCnt = 0;
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if (timer->info->cntmode == HWTIMER_CNTMODE_UP)
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{
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TIM_TimeBaseStructure.CntMode = TIM_CNT_MODE_UP;
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}
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else
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{
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TIM_TimeBaseStructure.CntMode = TIM_CNT_MODE_DOWN;
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}
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TIM_InitTimeBase(tim, &TIM_TimeBaseStructure);
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/* Enable the TIMx global Interrupt */
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NVIC_InitStructure.NVIC_IRQChannel = tim_device->tim_irqn;
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NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 2;
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NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
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NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
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NVIC_Init(&NVIC_InitStructure);
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TIM_ConfigInt(tim, TIM_INT_UPDATE, ENABLE);
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TIM_ClrIntPendingBit(tim, TIM_INT_UPDATE);
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LOG_D("%s init success", tim_device->name);
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}
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}
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static rt_err_t n32_timer_start(rt_hwtimer_t *timer, rt_uint32_t t, rt_hwtimer_mode_t opmode)
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{
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rt_err_t result = RT_EOK;
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TIM_Module *tim = RT_NULL;
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RT_ASSERT(timer != RT_NULL);
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tim = (TIM_Module *)timer->parent.user_data;
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/* set tim cnt */
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TIM_SetCnt(tim, 0);
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/* set tim arr */
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TIM_SetAutoReload(tim, t - 1);
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if (opmode == HWTIMER_MODE_ONESHOT)
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{
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/* set timer to single mode */
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TIM_SelectOnePulseMode(tim, TIM_OPMODE_SINGLE);
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}
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else
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{
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TIM_SelectOnePulseMode(tim, TIM_OPMODE_REPET);
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}
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/* start timer */
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TIM_Enable(tim, ENABLE);
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return result;
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}
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static void n32_timer_stop(rt_hwtimer_t *timer)
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{
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TIM_Module *tim = RT_NULL;
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RT_ASSERT(timer != RT_NULL);
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tim = (TIM_Module *)timer->parent.user_data;
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/* stop timer */
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TIM_Enable(tim, DISABLE);
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/* set tim cnt */
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TIM_SetCnt(tim, 0);
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}
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static rt_uint32_t n32_timer_counter_get(rt_hwtimer_t *timer)
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{
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TIM_Module *tim = RT_NULL;
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RT_ASSERT(timer != RT_NULL);
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tim = (TIM_Module *)timer->parent.user_data;
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return tim->CNT;
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}
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static rt_err_t n32_timer_ctrl(rt_hwtimer_t *timer, rt_uint32_t cmd, void *arg)
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{
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RCC_ClocksType RCC_ClockStruct;
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TIM_Module *tim = RT_NULL;
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rt_err_t result = RT_EOK;
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RT_ASSERT(timer != RT_NULL);
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RT_ASSERT(arg != RT_NULL);
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tim = (TIM_Module *)timer->parent.user_data;
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switch (cmd)
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{
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case HWTIMER_CTRL_FREQ_SET:
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{
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rt_uint32_t freq;
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rt_uint16_t val;
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/* set timer frequence */
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freq = *((rt_uint32_t *)arg);
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/* time init */
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RCC_GetClocksFreqValue(&RCC_ClockStruct);
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val = RCC_ClockStruct.SysclkFreq / freq;
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TIM_ConfigPrescaler(tim, val - 1, TIM_PSC_RELOAD_MODE_IMMEDIATE);
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}
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break;
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default:
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{
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result = -RT_ENOSYS;
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}
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break;
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}
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return result;
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}
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static const struct rt_hwtimer_info _info = TIM_DEV_INFO_CONFIG;
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static const struct rt_hwtimer_ops _ops =
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{
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.init = n32_timer_init,
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.start = n32_timer_start,
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.stop = n32_timer_stop,
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.count_get = n32_timer_counter_get,
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.control = n32_timer_ctrl,
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};
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#ifdef BSP_USING_HWTIM2
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void TIM2_IRQHandler(void)
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{
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/* enter interrupt */
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rt_interrupt_enter();
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if (TIM_GetIntStatus(TIM2, TIM_INT_UPDATE) == SET)
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{
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rt_device_hwtimer_isr(&n32_hwtimer_obj[TIM2_INDEX].time_device);
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TIM_ClrIntPendingBit(TIM2, TIM_INT_UPDATE);
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}
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/* leave interrupt */
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rt_interrupt_leave();
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}
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#endif
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#ifdef BSP_USING_HWTIM3
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void TIM3_IRQHandler(void)
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{
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/* enter interrupt */
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rt_interrupt_enter();
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if (TIM_GetIntStatus(TIM3, TIM_INT_UPDATE) == SET)
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{
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rt_device_hwtimer_isr(&n32_hwtimer_obj[TIM3_INDEX].time_device);
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TIM_ClrIntPendingBit(TIM3, TIM_INT_UPDATE);
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}
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/* leave interrupt */
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rt_interrupt_leave();
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}
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#endif
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#ifdef BSP_USING_HWTIM4
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void TIM4_IRQHandler(void)
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{
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/* enter interrupt */
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rt_interrupt_enter();
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if (TIM_GetIntStatus(TIM4, TIM_INT_UPDATE) == SET)
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{
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rt_device_hwtimer_isr(&n32_hwtimer_obj[TIM4_INDEX].time_device);
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TIM_ClrIntPendingBit(TIM4, TIM_INT_UPDATE);
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}
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/* leave interrupt */
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rt_interrupt_leave();
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}
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#endif
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#ifdef BSP_USING_HWTIM5
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void TIM5_IRQHandler(void)
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{
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/* enter interrupt */
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rt_interrupt_enter();
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if (TIM_GetIntStatus(TIM5, TIM_INT_UPDATE) == SET)
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{
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rt_device_hwtimer_isr(&n32_hwtimer_obj[TIM5_INDEX].time_device);
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TIM_ClrIntPendingBit(TIM5, TIM_INT_UPDATE);
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}
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/* leave interrupt */
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rt_interrupt_leave();
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}
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#endif
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#ifdef BSP_USING_HWTIM6
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void TIM6_IRQHandler(void)
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{
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/* enter interrupt */
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rt_interrupt_enter();
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if (TIM_GetIntStatus(TIM6, TIM_INT_UPDATE) == SET)
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{
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rt_device_hwtimer_isr(&n32_hwtimer_obj[TIM6_INDEX].time_device);
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TIM_ClrIntPendingBit(TIM6, TIM_INT_UPDATE);
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}
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/* leave interrupt */
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rt_interrupt_leave();
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}
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#endif
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#ifdef BSP_USING_HWTIM7
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void TIM7_IRQHandler(void)
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{
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/* enter interrupt */
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rt_interrupt_enter();
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if (TIM_GetIntStatus(TIM7, TIM_INT_UPDATE) == SET)
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{
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rt_device_hwtimer_isr(&n32_hwtimer_obj[TIM7_INDEX].time_device);
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TIM_ClrIntPendingBit(TIM7, TIM_INT_UPDATE);
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}
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/* leave interrupt */
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rt_interrupt_leave();
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}
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#endif
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static int rt_hw_hwtimer_init(void)
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{
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int i = 0;
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int result = RT_EOK;
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for (i = 0; i < sizeof(n32_hwtimer_obj) / sizeof(n32_hwtimer_obj[0]); i++)
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{
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n32_hwtimer_obj[i].time_device.info = &_info;
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n32_hwtimer_obj[i].time_device.ops = &_ops;
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if (rt_device_hwtimer_register(&n32_hwtimer_obj[i].time_device, n32_hwtimer_obj[i].name, n32_hwtimer_obj[i].tim_handle) == RT_EOK)
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{
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LOG_D("%s register success", n32_hwtimer_obj[i].name);
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}
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else
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{
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LOG_E("%s register failed", n32_hwtimer_obj[i].name);
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result = -RT_ERROR;
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}
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}
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return result;
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}
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INIT_BOARD_EXPORT(rt_hw_hwtimer_init);
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#endif /* BSP_USING_HWTIMER */
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