364 lines
16 KiB
C
364 lines
16 KiB
C
/*****************************************************************************
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* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
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*
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* This software component is licensed by HDSC under BSD 3-Clause license
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* (the "License"); You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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*/
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/******************************************************************************/
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/** \file hc32f460_dmac.h
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**
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** A detailed description is available at
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** @link DmacGroup DMAC description @endlink
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**
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** - 2018-11-18 CDT First version for Device Driver Library of DMAC.
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**
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******************************************************************************/
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#ifndef __HC32F460_DMAC_H__
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#define __HC32F460_DMAC_H__
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/*******************************************************************************
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* Include files
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******************************************************************************/
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#include "hc32_common.h"
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#include "ddl_config.h"
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#if (DDL_DMAC_ENABLE == DDL_ON)
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/* C binding of definitions if building with C++ compiler */
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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/**
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*******************************************************************************
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** \defgroup DmacGroup Direct Memory Access Control(DMAC)
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**
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******************************************************************************/
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//@{
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/*******************************************************************************
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* Global type definitions ('typedef')
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******************************************************************************/
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/**
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*******************************************************************************
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** \brief DMA Channel
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**
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******************************************************************************/
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typedef enum en_dma_channel
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{
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DmaCh0 = 0u, ///< DMA channel 0
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DmaCh1 = 1u, ///< DMA channel 1
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DmaCh2 = 2u, ///< DMA channel 2
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DmaCh3 = 3u, ///< DMA channel 3
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DmaChMax = 4u ///< DMA channel max
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}en_dma_channel_t;
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/**
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*******************************************************************************
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** \brief DMA transfer data width
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**
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******************************************************************************/
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typedef enum en_dma_transfer_width
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{
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Dma8Bit = 0u, ///< 8 bit transfer via DMA
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Dma16Bit = 1u, ///< 16 bit transfer via DMA
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Dma32Bit = 2u ///< 32 bit transfer via DMA
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}en_dma_transfer_width_t;
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/**
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*******************************************************************************
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** \brief DMA flag
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**
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******************************************************************************/
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typedef enum en_dma_flag
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{
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DmaTransferComplete = 0u, ///< DMA transfer complete
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DmaBlockComplete = 1u, ///< DMA block transfer complete
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DmaTransferErr = 2u, ///< DMA transfer error
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DmaReqErr = 3u, ///< DMA transfer request error
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DmaFlagMax = 4u
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}en_dma_flag_t;
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/**
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*******************************************************************************
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** \brief DMA address mode
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**
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******************************************************************************/
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typedef enum en_dma_address_mode
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{
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AddressFix = 0u, ///< Address fixed
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AddressIncrease = 1u, ///< Address increased
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AddressDecrease = 2u, ///< Address decreased
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}en_dma_address_mode_t;
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/**
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*******************************************************************************
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** \brief DMA link list pointer mode
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**
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******************************************************************************/
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typedef enum en_dma_llp_mode
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{
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LlpWaitNextReq = 0u, ///< DMA trigger transfer after wait next request
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LlpRunNow = 1u, ///< DMA trigger transfer now
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}en_dma_llp_mode_t;
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/**
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*******************************************************************************
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** \brief DMA interrupt selection
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**
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******************************************************************************/
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typedef enum en_dma_irq_sel
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{
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TrnErrIrq = 0u, ///< Select DMA transfer error interrupt
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TrnReqErrIrq = 1u, ///< Select DMA transfer req over error interrupt
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TrnCpltIrq = 2u, ///< Select DMA transfer completion interrupt
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BlkTrnCpltIrq = 3u, ///< Select DMA block completion interrupt
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DmaIrqSelMax = 4u
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}en_dma_irq_sel_t;
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/**
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*******************************************************************************
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** \brief DMA re_config count mode
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**
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******************************************************************************/
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typedef enum en_dma_recfg_cnt_mode
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{
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CntFix = 0u, ///< Fix
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CntSrcAddr = 1u, ///< Source address mode
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CntDesAddr = 2u, ///< Destination address mode
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}en_dma_recfg_cnt_mode_t;
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/**
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*******************************************************************************
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** \brief DMA re_config destination address mode
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**
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******************************************************************************/
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typedef enum en_dma_recfg_daddr_mode
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{
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DaddrFix = 0u, ///< Fix
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DaddrNseq = 1u, ///< No_sequence address
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DaddrRep = 2u, ///< Repeat address
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}en_dma_recfg_daddr_mode_t;
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/**
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*******************************************************************************
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** \brief DMA re_config source address mode
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**
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******************************************************************************/
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typedef enum en_dma_recfg_saddr_mode
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{
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SaddrFix = 0u, ///< Fix
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SaddrNseq = 1u, ///< No_sequence address
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SaddrRep = 2u, ///< Repeat address
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}en_dma_recfg_saddr_mode_t;
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/**
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*******************************************************************************
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** \brief DMA channel status
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**
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******************************************************************************/
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typedef enum en_dma_ch_flag
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{
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DmaSta = 0u, ///< DMA status.
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ReCfgSta = 1u, ///< DMA re_configuration status.
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DmaCh0Sta = 2u, ///< DMA channel 0 status.
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DmaCh1Sta = 3u, ///< DMA channel 1 status.
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DmaCh2Sta = 4u, ///< DMA channel 2 status.
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DmaCh3Sta = 5u, ///< DMA channel 3 status.
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}en_dma_ch_flag_t;
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/**
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*******************************************************************************
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** \brief DMA common trigger source select
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**
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******************************************************************************/
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typedef enum en_dma_com_trigger
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{
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DmaComTrigger_1 = 0x1, ///< Select common trigger 1.
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DmaComTrigger_2 = 0x2, ///< Select common trigger 2.
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DmaComTrigger_1_2 = 0x3, ///< Select common trigger 1 and 2.
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} en_dma_com_trigger_t;
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/**
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*******************************************************************************
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** \brief DMA llp descriptor
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**
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******************************************************************************/
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typedef struct stc_dma_llp_descriptor
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{
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uint32_t SARx; ///< DMA source address register
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uint32_t DARx; ///< DMA destination address register
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union
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{
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uint32_t DTCTLx;
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stc_dma_dtctl_field_t DTCTLx_f; ///< DMA data control register
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};
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union
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{
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uint32_t RPTx;
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stc_dma_rpt_field_t RPTx_f; ///< DMA repeat control register
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};
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union
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{
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uint32_t SNSEQCTLx;
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stc_dma_snseqctl_field_t SNSEQCTLx_f; ///< DMA source no-sequence control register
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};
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union
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{
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__IO uint32_t DNSEQCTLx;
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stc_dma_dnseqctl_field_t DNSEQCTLx_f; ///< DMA destination no-sequence control register
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};
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union
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{
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uint32_t LLPx;
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stc_dma_llp_field_t LLPx_f; ///< DMA link-list-pointer register
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};
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union
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{
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uint32_t CHxCTL;
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stc_dma_ch0ctl_field_t CHxCTL_f; ///< DMA channel control register
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};
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}stc_dma_llp_descriptor_t;
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/**
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*******************************************************************************
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** \brief DMA no-sequence function configuration
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**
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******************************************************************************/
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typedef struct stc_dma_nseq_cfg
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{
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uint32_t u32Offset; ///< DMA no-sequence offset.
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uint16_t u16Cnt; ///< DMA no-sequence count.
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}stc_dma_nseq_cfg_t;
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/**
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*******************************************************************************
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** \brief DMA no-sequence function configuration
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**
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******************************************************************************/
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typedef struct stc_dma_nseqb_cfg
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{
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uint32_t u32NseqDist; ///< DMA no-sequence district interval.
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uint16_t u16CntB; ///< DMA no-sequence count.
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}stc_dma_nseqb_cfg_t;
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/**
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*******************************************************************************
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** \brief DMA re_config configuration
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**
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******************************************************************************/
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typedef struct stc_dma_recfg_ctl
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{
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uint16_t u16SrcRptBSize; ///< The source repeat size.
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uint16_t u16DesRptBSize; ///< The destination repeat size.
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en_dma_recfg_saddr_mode_t enSaddrMd; ///< DMA re_config source address mode.
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en_dma_recfg_daddr_mode_t enDaddrMd; ///< DMA re_config destination address mode.
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en_dma_recfg_cnt_mode_t enCntMd; ///< DMA re_config count mode.
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stc_dma_nseq_cfg_t stcSrcNseqBCfg; ///< The source no_sequence re_config.
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stc_dma_nseq_cfg_t stcDesNseqBCfg; ///< The destination no_sequence re_config.
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}stc_dma_recfg_ctl_t;
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/**
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*******************************************************************************
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** \brief DMA channel configuration
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**
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******************************************************************************/
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typedef struct stc_dma_ch_cfg
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{
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en_dma_address_mode_t enSrcInc; ///< DMA source address update mode.
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en_dma_address_mode_t enDesInc; ///< DMA destination address update mode.
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en_functional_state_t enSrcRptEn; ///< Enable source repeat function or not.
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en_functional_state_t enDesRptEn; ///< Enable destination repeat function or not.
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en_functional_state_t enSrcNseqEn; ///< Enable source no_sequence function or not.
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en_functional_state_t enDesNseqEn; ///< Enable destination no_sequence function or not.
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en_dma_transfer_width_t enTrnWidth; ///< DMA transfer data width.
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en_functional_state_t enLlpEn; ///< Enable linked list pointer function or not.
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en_dma_llp_mode_t enLlpMd; ///< Dma linked list pointer mode.
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en_functional_state_t enIntEn; ///< Enable interrupt function or not.
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}stc_dma_ch_cfg_t;
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/**
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*******************************************************************************
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** \brief DMA configuration
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**
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******************************************************************************/
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typedef struct stc_dma_config
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{
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uint16_t u16BlockSize; ///< Transfer block size = 1024, when 0 is set.
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uint16_t u16TransferCnt; ///< Transfer counter.
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uint32_t u32SrcAddr; ///< The source address.
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uint32_t u32DesAddr; ///< The destination address.
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uint16_t u16SrcRptSize; ///< The source repeat size.
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uint16_t u16DesRptSize; ///< The destination repeat size.
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uint32_t u32DmaLlp; ///< The Dma linked list pointer address
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stc_dma_nseq_cfg_t stcSrcNseqCfg; ///< The source no_sequence configuration.
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stc_dma_nseq_cfg_t stcDesNseqCfg; ///< The destination no_sequence configuration.
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stc_dma_ch_cfg_t stcDmaChCfg; ///< The Dma channel configuration.
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}stc_dma_config_t;
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/*******************************************************************************
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* Global pre-processor symbols/macros ('#define')
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******************************************************************************/
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/*******************************************************************************
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* Global variable definitions ('extern')
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******************************************************************************/
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/*******************************************************************************
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* Global function prototypes (definition in C source)
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******************************************************************************/
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void DMA_Cmd(M4_DMA_TypeDef* pstcDmaReg, en_functional_state_t enNewState);
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en_result_t DMA_EnableIrq(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, en_dma_irq_sel_t enIrqSel);
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en_result_t DMA_DisableIrq(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, en_dma_irq_sel_t enIrqSel);
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en_flag_status_t DMA_GetIrqFlag(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, en_dma_irq_sel_t enIrqSel);
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en_result_t DMA_ClearIrqFlag(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, en_dma_irq_sel_t enIrqSel);
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en_result_t DMA_ChannelCmd(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, en_functional_state_t enNewState);
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void DMA_InitReConfig(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, const stc_dma_recfg_ctl_t* pstcDmaReCfg);
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void DMA_ReCfgCmd(M4_DMA_TypeDef* pstcDmaReg,en_functional_state_t enNewState);
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en_flag_status_t DMA_GetChFlag(M4_DMA_TypeDef* pstcDmaReg, en_dma_ch_flag_t enDmaChFlag);
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en_result_t DMA_SetSrcAddress(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, uint32_t u32Address);
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en_result_t DMA_SetDesAddress(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, uint32_t u32Address);
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en_result_t DMA_SetBlockSize(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, uint16_t u16BlkSize);
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en_result_t DMA_SetTransferCnt(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, uint16_t u16TrnCnt);
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en_result_t DMA_SetSrcRptSize(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, uint16_t u16Size);
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en_result_t DMA_SetDesRptSize(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, uint16_t u16Size);
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en_result_t DMA_SetSrcRptbSize(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, uint16_t u16Size);
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en_result_t DMA_SetDesRptbSize(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, uint16_t u16Size);
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en_result_t DMA_SetSrcNseqCfg(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, const stc_dma_nseq_cfg_t* pstcSrcNseqCfg);
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en_result_t DMA_SetSrcNseqBCfg(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, const stc_dma_nseqb_cfg_t* pstcSrcNseqBCfg);
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en_result_t DMA_SetDesNseqCfg(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, const stc_dma_nseq_cfg_t* pstDesNseqCfg);
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en_result_t DMA_SetDesNseqBCfg(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, const stc_dma_nseqb_cfg_t* pstDesNseqBCfg);
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en_result_t DMA_SetLLP(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, uint32_t u32Pointer);
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void DMA_SetTriggerSrc(const M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, en_event_src_t enSrc);
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void DMA_SetReConfigTriggerSrc(en_event_src_t enSrc);
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void DMA_ComTriggerCmd(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, en_dma_com_trigger_t enComTrigger, en_functional_state_t enNewState);
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void DMA_ReConfigComTriggerCmd(en_dma_com_trigger_t enComTrigger, en_functional_state_t enNewState);
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void DMA_ChannelCfg(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, const stc_dma_ch_cfg_t* pstcChCfg);
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void DMA_InitChannel(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch, const stc_dma_config_t* pstcDmaCfg);
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void DMA_DeInit(M4_DMA_TypeDef* pstcDmaReg, uint8_t u8Ch);
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//@} // DmacGroup
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#ifdef __cplusplus
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}
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#endif
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#endif /* DDL_DMAC_ENABLE */
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#endif /* __HC32F460_DMAC_H__*/
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/*******************************************************************************
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* EOF (not truncated)
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******************************************************************************/
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