147 lines
5.8 KiB
C
147 lines
5.8 KiB
C
/*
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* The Clear BSD License
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* Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
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* Copyright 2016-2017 NXP
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted (subject to the limitations in the disclaimer below) provided
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* that the following conditions are met:
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*
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* o Redistributions of source code must retain the above copyright notice, this list
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* of conditions and the following disclaimer.
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*
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* o Redistributions in binary form must reproduce the above copyright notice, this
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* list of conditions and the following disclaimer in the documentation and/or
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* other materials provided with the distribution.
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*
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* o Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "fsl_crc.h"
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/*******************************************************************************
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* Definitions
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******************************************************************************/
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/* Component ID definition, used by tools. */
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#ifndef FSL_COMPONENT_ID
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#define FSL_COMPONENT_ID "platform.drivers.lpc_crc"
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#endif
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#if defined(CRC_DRIVER_USE_CRC16_CCITT_FALSE_AS_DEFAULT) && CRC_DRIVER_USE_CRC16_CCITT_FALSE_AS_DEFAULT
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/* @brief Default user configuration structure for CRC-CCITT */
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#define CRC_DRIVER_DEFAULT_POLYNOMIAL kCRC_Polynomial_CRC_CCITT
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/*< CRC-CCIT polynomial x^16 + x^12 + x^5 + x^0 */
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#define CRC_DRIVER_DEFAULT_REVERSE_IN false
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/*< Default is no bit reverse */
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#define CRC_DRIVER_DEFAULT_COMPLEMENT_IN false
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/*< Default is without complement of written data */
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#define CRC_DRIVER_DEFAULT_REVERSE_OUT false
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/*< Default is no bit reverse */
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#define CRC_DRIVER_DEFAULT_COMPLEMENT_OUT false
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/*< Default is without complement of CRC data register read data */
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#define CRC_DRIVER_DEFAULT_SEED 0xFFFFU
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/*< Default initial checksum */
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#endif /* CRC_DRIVER_USE_CRC16_CCITT_FALSE_AS_DEFAULT */
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/*******************************************************************************
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* Code
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******************************************************************************/
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void CRC_Init(CRC_Type *base, const crc_config_t *config)
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{
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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/* enable clock to CRC */
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CLOCK_EnableClock(kCLOCK_Crc);
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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/* configure CRC module and write the seed */
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base->MODE = 0 | CRC_MODE_CRC_POLY(config->polynomial) | CRC_MODE_BIT_RVS_WR(config->reverseIn) |
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CRC_MODE_CMPL_WR(config->complementIn) | CRC_MODE_BIT_RVS_SUM(config->reverseOut) |
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CRC_MODE_CMPL_SUM(config->complementOut);
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base->SEED = config->seed;
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}
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void CRC_GetDefaultConfig(crc_config_t *config)
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{
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static const crc_config_t default_config = {CRC_DRIVER_DEFAULT_POLYNOMIAL, CRC_DRIVER_DEFAULT_REVERSE_IN,
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CRC_DRIVER_DEFAULT_COMPLEMENT_IN, CRC_DRIVER_DEFAULT_REVERSE_OUT,
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CRC_DRIVER_DEFAULT_COMPLEMENT_OUT, CRC_DRIVER_DEFAULT_SEED};
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*config = default_config;
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}
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void CRC_Reset(CRC_Type *base)
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{
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crc_config_t config;
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CRC_GetDefaultConfig(&config);
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CRC_Init(base, &config);
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}
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void CRC_GetConfig(CRC_Type *base, crc_config_t *config)
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{
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/* extract CRC mode settings */
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uint32_t mode = base->MODE;
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config->polynomial = (crc_polynomial_t)((mode & CRC_MODE_CRC_POLY_MASK) >> CRC_MODE_CRC_POLY_SHIFT);
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config->reverseIn = (bool)(mode & CRC_MODE_BIT_RVS_WR_MASK);
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config->complementIn = (bool)(mode & CRC_MODE_CMPL_WR_MASK);
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config->reverseOut = (bool)(mode & CRC_MODE_BIT_RVS_SUM_MASK);
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config->complementOut = (bool)(mode & CRC_MODE_CMPL_SUM_MASK);
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/* reset CRC sum bit reverse and 1's complement setting, so its value can be used as a seed */
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base->MODE = mode & ~((1U << CRC_MODE_BIT_RVS_SUM_SHIFT) | (1U << CRC_MODE_CMPL_SUM_SHIFT));
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/* now we can obtain intermediate raw CRC sum value */
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config->seed = base->SUM;
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/* restore original CRC sum bit reverse and 1's complement setting */
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base->MODE = mode;
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}
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void CRC_WriteData(CRC_Type *base, const uint8_t *data, size_t dataSize)
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{
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const uint32_t *data32;
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/* 8-bit reads and writes till source address is aligned 4 bytes */
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while ((dataSize) && ((uint32_t)data & 3U))
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{
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*((__O uint8_t *)&(base->WR_DATA)) = *data;
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data++;
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dataSize--;
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}
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/* use 32-bit reads and writes as long as possible */
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data32 = (const uint32_t *)data;
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while (dataSize >= sizeof(uint32_t))
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{
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*((__O uint32_t *)&(base->WR_DATA)) = *data32;
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data32++;
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dataSize -= sizeof(uint32_t);
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}
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data = (const uint8_t *)data32;
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/* 8-bit reads and writes till end of data buffer */
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while (dataSize)
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{
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*((__O uint8_t *)&(base->WR_DATA)) = *data;
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data++;
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dataSize--;
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}
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}
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