193 lines
6.1 KiB
C
193 lines
6.1 KiB
C
/*
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* The Clear BSD License
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* Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
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* Copyright 2016 NXP
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* All rights reserved.
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*
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted (subject to the limitations in the disclaimer below) provided
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* that the following conditions are met:
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*
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* o Redistributions of source code must retain the above copyright notice, this list
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* of conditions and the following disclaimer.
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*
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* o Redistributions in binary form must reproduce the above copyright notice, this
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* list of conditions and the following disclaimer in the documentation and/or
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* other materials provided with the distribution.
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*
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* o Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "fsl_common.h"
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#define SDK_MEM_MAGIC_NUMBER 12345U
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typedef struct _mem_align_control_block
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{
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uint16_t identifier; /*!< Identifier for the memory control block. */
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uint16_t offset; /*!< offset from aligned adress to real address */
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} mem_align_cb_t;
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/* Component ID definition, used by tools. */
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#ifndef FSL_COMPONENT_ID
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#define FSL_COMPONENT_ID "platform.drivers.common"
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#endif
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#ifndef __GIC_PRIO_BITS
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#if defined(ENABLE_RAM_VECTOR_TABLE)
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uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler)
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{
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/* Addresses for VECTOR_TABLE and VECTOR_RAM come from the linker file */
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#if defined(__CC_ARM)
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extern uint32_t Image$$VECTOR_ROM$$Base[];
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extern uint32_t Image$$VECTOR_RAM$$Base[];
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extern uint32_t Image$$RW_m_data$$Base[];
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#define __VECTOR_TABLE Image$$VECTOR_ROM$$Base
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#define __VECTOR_RAM Image$$VECTOR_RAM$$Base
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#define __RAM_VECTOR_TABLE_SIZE (((uint32_t)Image$$RW_m_data$$Base - (uint32_t)Image$$VECTOR_RAM$$Base))
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#elif defined(__ICCARM__)
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extern uint32_t __RAM_VECTOR_TABLE_SIZE[];
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extern uint32_t __VECTOR_TABLE[];
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extern uint32_t __VECTOR_RAM[];
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#elif defined(__GNUC__)
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extern uint32_t __VECTOR_TABLE[];
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extern uint32_t __VECTOR_RAM[];
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extern uint32_t __RAM_VECTOR_TABLE_SIZE_BYTES[];
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uint32_t __RAM_VECTOR_TABLE_SIZE = (uint32_t)(__RAM_VECTOR_TABLE_SIZE_BYTES);
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#endif /* defined(__CC_ARM) */
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uint32_t n;
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uint32_t ret;
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uint32_t irqMaskValue;
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irqMaskValue = DisableGlobalIRQ();
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if (SCB->VTOR != (uint32_t)__VECTOR_RAM)
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{
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/* Copy the vector table from ROM to RAM */
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for (n = 0; n < ((uint32_t)__RAM_VECTOR_TABLE_SIZE) / sizeof(uint32_t); n++)
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{
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__VECTOR_RAM[n] = __VECTOR_TABLE[n];
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}
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/* Point the VTOR to the position of vector table */
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SCB->VTOR = (uint32_t)__VECTOR_RAM;
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}
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ret = __VECTOR_RAM[irq + 16];
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/* make sure the __VECTOR_RAM is noncachable */
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__VECTOR_RAM[irq + 16] = irqHandler;
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EnableGlobalIRQ(irqMaskValue);
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/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
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exception return operation might vector to incorrect interrupt */
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#if defined __CORTEX_M && (__CORTEX_M == 4U)
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__DSB();
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#endif
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return ret;
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}
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#endif /* ENABLE_RAM_VECTOR_TABLE. */
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#endif /* __GIC_PRIO_BITS. */
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#ifndef QN908XC_SERIES
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#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0))
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void EnableDeepSleepIRQ(IRQn_Type interrupt)
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{
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uint32_t intNumber = (uint32_t)interrupt;
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#if (defined(FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS) && (FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS == 1))
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{
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SYSCON->STARTERP1 = 1u << intNumber;
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}
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#else
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{
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uint32_t index = 0;
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while (intNumber >= 32u)
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{
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index++;
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intNumber -= 32u;
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}
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SYSCON->STARTERSET[index] = 1u << intNumber;
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}
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#endif /* FSL_FEATURE_STARTER_DISCONTINUOUS */
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EnableIRQ(interrupt); /* also enable interrupt at NVIC */
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}
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void DisableDeepSleepIRQ(IRQn_Type interrupt)
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{
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uint32_t intNumber = (uint32_t)interrupt;
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DisableIRQ(interrupt); /* also disable interrupt at NVIC */
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#if (defined(FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS) && (FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS == 1))
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{
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SYSCON->STARTERP1 &= ~(1u << intNumber);
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}
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#else
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{
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uint32_t index = 0;
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while (intNumber >= 32u)
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{
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index++;
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intNumber -= 32u;
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}
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SYSCON->STARTERCLR[index] = 1u << intNumber;
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}
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#endif /* FSL_FEATURE_STARTER_DISCONTINUOUS */
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}
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#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */
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#endif /* QN908XC_SERIES */
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void *SDK_Malloc(size_t size, size_t alignbytes)
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{
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mem_align_cb_t *p_cb = NULL;
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uint32_t alignedsize = SDK_SIZEALIGN(size, alignbytes) + alignbytes + sizeof(mem_align_cb_t);
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void *p_align_addr, *p_addr = malloc(alignedsize);
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if (!p_addr)
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{
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return NULL;
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}
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p_align_addr = (void *)SDK_SIZEALIGN((uint32_t)p_addr + sizeof(mem_align_cb_t), alignbytes);
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p_cb = (mem_align_cb_t *)((uint32_t)p_align_addr - 4);
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p_cb->identifier = SDK_MEM_MAGIC_NUMBER;
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p_cb->offset = (uint32_t)p_align_addr - (uint32_t)p_addr;
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return (void *)p_align_addr;
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}
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void SDK_Free(void *ptr)
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{
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mem_align_cb_t *p_cb = (mem_align_cb_t *)((uint32_t)ptr - 4);
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if (p_cb->identifier != SDK_MEM_MAGIC_NUMBER)
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{
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return;
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}
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free((void *)((uint32_t)ptr - p_cb->offset));
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}
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