352 lines
12 KiB
C
352 lines
12 KiB
C
/*
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* @brief SSP Registers and control functions
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*
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* @note
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* Copyright(C) NXP Semiconductors, 2012
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* All rights reserved.
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*
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* @par
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* Software that is described herein is for illustrative purposes only
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* which provides customers with programming information regarding the
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* LPC products. This software is supplied "AS IS" without any warranties of
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* any kind, and NXP Semiconductors and its licensor disclaim any and
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* all warranties, express or implied, including all implied warranties of
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* merchantability, fitness for a particular purpose and non-infringement of
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* intellectual property rights. NXP Semiconductors assumes no responsibility
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* or liability for the use of the software, conveys no license or rights under any
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* patent, copyright, mask work right, or any other intellectual property rights in
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* or to any products. NXP Semiconductors reserves the right to make changes
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* in the software without notification. NXP Semiconductors also makes no
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* representation or warranty that such application will be suitable for the
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* specified use without further testing or modification.
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*
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* @par
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* Permission to use, copy, modify, and distribute this software and its
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* documentation is hereby granted, under NXP Semiconductors' and its
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* licensor's relevant copyrights in the software, without fee, provided that it
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* is used in conjunction with NXP Semiconductors microcontrollers. This
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* copyright, permission, and disclaimer notice must appear in all copies of
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* this code.
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*/
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#ifndef __SSP_001_H_
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#define __SSP_001_H_
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#include "sys_config.h"
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#include "cmsis.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** @defgroup IP_SSP_001 IP: SSP register block and driver
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* @ingroup IP_Drivers
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* @{
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*/
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/**
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* @brief SSP register block structure
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*/
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typedef struct { /*!< SSPn Structure */
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__IO uint32_t CR0; /*!< Control Register 0. Selects the serial clock rate, bus type, and data size. */
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__IO uint32_t CR1; /*!< Control Register 1. Selects master/slave and other modes. */
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__IO uint32_t DR; /*!< Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO. */
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__I uint32_t SR; /*!< Status Register */
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__IO uint32_t CPSR; /*!< Clock Prescale Register */
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__IO uint32_t IMSC; /*!< Interrupt Mask Set and Clear Register */
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__I uint32_t RIS; /*!< Raw Interrupt Status Register */
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__I uint32_t MIS; /*!< Masked Interrupt Status Register */
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__O uint32_t ICR; /*!< SSPICR Interrupt Clear Register */
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#if !defined(CHIP_LPC111X_CXX) && !defined(CHIP_LPC11UXX) /* no DMA on LPC11xx or LPC11Uxx */
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__IO uint32_t DMACR; /*!< SSPn DMA control register */
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#endif
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} IP_SSP_001_Type;
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/**
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* Macro defines for CR0 register
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*/
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/** SSP data size select, must be 4 bits to 16 bits */
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#define SSP_CR0_DSS(n) ((uint32_t) ((n) & 0xF))
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/** SSP control 0 Motorola SPI mode */
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#define SSP_CR0_FRF_SPI ((uint32_t) (0 << 4))
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/** SSP control 0 TI synchronous serial mode */
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#define SSP_CR0_FRF_TI ((uint32_t) (1 << 4))
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/** SSP control 0 National Micro-wire mode */
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#define SSP_CR0_FRF_MICROWIRE ((uint32_t) (2 << 4))
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/** SPI clock polarity bit (used in SPI mode only), (1) = maintains the
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bus clock high between frames, (0) = low */
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#define SSP_CR0_CPOL_LO ((uint32_t) (0))
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#define SSP_CR0_CPOL_HI ((uint32_t) (1 << 6))
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/** SPI clock out phase bit (used in SPI mode only), (1) = captures data
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on the second clock transition of the frame, (0) = first */
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#define SSP_CR0_CPHA_FIRST ((uint32_t) (0))
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#define SSP_CR0_CPHA_SECOND ((uint32_t) (1 << 7))
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/** SSP serial clock rate value load macro, divider rate is
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PERIPH_CLK / (cpsr * (SCR + 1)) */
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#define SSP_CR0_SCR(n) ((uint32_t) ((n & 0xFF) << 8))
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/** SSP CR0 bit mask */
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#define SSP_CR0_BITMASK ((uint32_t) (0xFFFF))
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/** SSP CR0 bit mask */
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#define SSP_CR0_BITMASK ((uint32_t) (0xFFFF))
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/** SSP serial clock rate value load macro, divider rate is
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PERIPH_CLK / (cpsr * (SCR + 1)) */
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#define SSP_CR0_SCR(n) ((uint32_t) ((n & 0xFF) << 8))
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/**
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* Macro defines for CR1 register
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*/
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/** SSP control 1 loopback mode enable bit */
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#define SSP_CR1_LBM_EN ((uint32_t) (1 << 0))
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/** SSP control 1 enable bit */
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#define SSP_CR1_SSP_EN ((uint32_t) (1 << 1))
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/** SSP control 1 slave enable */
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#define SSP_CR1_SLAVE_EN ((uint32_t) (1 << 2))
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#define SSP_CR1_MASTER_EN ((uint32_t) (0))
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/** SSP control 1 slave out disable bit, disables transmit line in slave
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mode */
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#define SSP_CR1_SO_DISABLE ((uint32_t) (1 << 3))
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/** SSP CR1 bit mask */
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#define SSP_CR1_BITMASK ((uint32_t) (0x0F))
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/** SSP CPSR bit mask */
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#define SSP_CPSR_BITMASK ((uint32_t) (0xFF))
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/**
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* Macro defines for DR register
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*/
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/** SSP data bit mask */
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#define SSP_DR_BITMASK(n) ((n) & 0xFFFF)
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/**
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* Macro defines for SR register
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*/
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/** SSP SR bit mask */
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#define SSP_SR_BITMASK ((uint32_t) (0x1F))
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/** ICR bit mask */
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#define SSP_ICR_BITMASK ((uint32_t) (0x03))
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/**
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* @brief SSP Type of Status
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*/
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typedef enum {
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SSP_STAT_TFE = ((uint32_t)(1 << 0)),/**< TX FIFO Empty */
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SSP_STAT_TNF = ((uint32_t)(1 << 1)),/**< TX FIFO not full */
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SSP_STAT_RNE = ((uint32_t)(1 << 2)),/**< RX FIFO not empty */
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SSP_STAT_RFF = ((uint32_t)(1 << 3)),/**< RX FIFO full */
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SSP_STAT_BSY = ((uint32_t)(1 << 4)),/**< SSP Busy */
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} SSP_Status_Type;
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/**
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* @brief SSP Type of Interrupt Mask
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*/
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typedef enum {
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SSP_RORIM = ((uint32_t)(1 << 0)), /**< Overun */
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SSP_RTIM = ((uint32_t)(1 << 1)),/**< TimeOut */
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SSP_RXIM = ((uint32_t)(1 << 2)),/**< Rx FIFO is at least half full */
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SSP_TXIM = ((uint32_t)(1 << 3)),/**< Tx FIFO is at least half empty */
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SSP_INT_MASK_BITMASK = ((uint32_t)(0xF)),
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} SSP_Int_Mask_Type;
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/**
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* @brief SSP Type of Mask Interrupt Status
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*/
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typedef enum {
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SSP_RORMIS = ((uint32_t)(1 << 0)), /**< Overun */
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SSP_RTMIS = ((uint32_t)(1 << 1)), /**< TimeOut */
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SSP_RXMIS = ((uint32_t)(1 << 2)), /**< Rx FIFO is at least half full */
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SSP_TXMIS = ((uint32_t)(1 << 3)), /**< Tx FIFO is at least half empty */
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SSP_MASK_INT_STAT_BITMASK = ((uint32_t)(0xF)),
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} SSP_Mask_Int_Status_Type;
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/**
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* @brief SSP Type of Raw Interrupt Status
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*/
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typedef enum {
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SSP_RORRIS = ((uint32_t)(1 << 0)), /**< Overun */
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SSP_RTRIS = ((uint32_t)(1 << 1)), /**< TimeOut */
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SSP_RXRIS = ((uint32_t)(1 << 2)), /**< Rx FIFO is at least half full */
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SSP_TXRIS = ((uint32_t)(1 << 3)), /**< Tx FIFO is at least half empty */
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SSP_RAW_INT_STAT_BITMASK = ((uint32_t)(0xF)),
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} SSP_Raw_Int_Status_Type;
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typedef enum {
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SSP_RORIC = 0x0,
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SSP_RTIC = 0x1,
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SSP_INT_CLEAR_BITMASK = 0x3,
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} SSP_Int_Clear_Type;
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typedef enum SSP_DMA_Type {
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SSP_DMA_RX = (1u), /**< DMA RX Enable */
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SSP_DMA_TX = (1u << 1), /**< DMA TX Enable */
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} SSP_DMA_Type;
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/**
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* @brief Disable SSP operation
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* @param pSSP : The base of SSP peripheral on the chip
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* @return Nothing
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* The SSP controller is disabled
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*/
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void IP_SSP_DeInit(IP_SSP_001_Type *pSSP);
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/**
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* @brief Enable/Disable SSP operation
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* @param pSSP : The base of SSP peripheral on the chip
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* @param NewState : New state, ENABLE or DISABLE
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* @return Nothing
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*/
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void IP_SSP_Cmd(IP_SSP_001_Type *pSSP, FunctionalState NewState);
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/**
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* @brief Enable/Disable loopback mode
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* @param pSSP : The base of SSP peripheral on the chip
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* @param NewState : New state, ENABLE or DISABLE
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* @return Nothing
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* Serial input is taken from the serial output (MOSI or MISO) rather
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* than the serial input pin
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*/
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void IP_SSP_LoopBackCmd(IP_SSP_001_Type *pSSP, FunctionalState NewState);
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/**
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* @brief Get the current status of SSP controller
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* @param pSSP : The base of SSP peripheral on the chip
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* @param Stat : Type of status, should be :
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* - SSP_STAT_TFE
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* - SSP_STAT_TNF
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* - SSP_STAT_RNE
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* - SSP_STAT_RFF
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* - SSP_STAT_BSY
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* @return SSP controller status, SET or RESET
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*/
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FlagStatus IP_SSP_GetStatus(IP_SSP_001_Type *pSSP, SSP_Status_Type Stat);
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/**
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* @brief Get the masked interrupt status
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* @param pSSP : The base of SSP peripheral on the chip
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* @return SSP Masked Interrupt Status Register value
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* The return value contains a 1 for each interrupt condition that is asserted and enabled (masked)
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*/
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uint32_t IP_SSP_GetIntStatus(IP_SSP_001_Type *pSSP);
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/**
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* @brief Get the raw interrupt status
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* @param pSSP : The base of SSP peripheral on the chip
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* @param RawInt : Interrupt condition to be get status, shoud be :
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* - SSP_RORRIS
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* - SSP_RTRIS
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* - SSP_RXRIS
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* - SSP_TXRIS
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* @return Raw interrupt status corresponding to interrupt condition , SET or RESET
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* Get the status of each interrupt condition ,regardless of whether or not the interrupt is enabled
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*/
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IntStatus IP_SSP_GetRawIntStatus(IP_SSP_001_Type *pSSP, SSP_Raw_Int_Status_Type RawInt);
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/**
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* @brief Get the number of bits transferred in each frame
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* @param pSSP : The base of SSP peripheral on the chip
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* @return the number of bits transferred in each frame minus one
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* The return value is 0x03 -> 0xF corresponding to 4bit -> 16bit transfer
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*/
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uint8_t IP_SSP_GetDataSize(IP_SSP_001_Type *pSSP);
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/**
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* @brief Clear the corresponding interrupt condition(s) in the SSP controller
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* @param pSSP : The base of SSP peripheral on the chip
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* @param IntClear: Type of cleared interrupt, should be :
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* - SSP_RORIC
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* - SSP_RTIC
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* @return Nothing
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* Software can clear one or more interrupt condition(s) in the SSP controller
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*/
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void IP_SSP_ClearIntPending(IP_SSP_001_Type *pSSP, SSP_Int_Clear_Type IntClear);
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/**
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* @brief Enable/Disable interrupt for the SSP
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* @param pSSP : The base of SSP peripheral on the chip
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* @param IntType : Type of interrupt condition to be enable/disable, should be :
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* - SSP_RORIM
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* - SSP_RTIM
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* - SSP_RXIM
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* - SSP_TXIM
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* @param NewState : New state, ENABLE or DISABLE
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* @return Nothing
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*/
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void IP_SSP_Int_Enable(IP_SSP_001_Type *pSSP, SSP_Int_Mask_Type IntType, FunctionalState NewState);
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/**
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* @brief Get received SSP data
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* @param pSSP : The base of SSP peripheral on the chip
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* @return SSP 16-bit data received
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*/
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uint16_t IP_SSP_ReceiveFrame(IP_SSP_001_Type *pSSP);
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/**
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* @brief Send SSP 16-bit data
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* @param pSSP : The base of SSP peripheral on the chip
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* @param tx_data : SSP 16-bit data to be transmited
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* @return Nothing
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*/
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void IP_SSP_SendFrame(IP_SSP_001_Type *pSSP, uint16_t tx_data);
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/**
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* @brief Set up output clocks per bit for SSP bus
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* @param pSSP : The base of SSP peripheral on the chip
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* @param clk_rate fs: The number of prescaler-output clocks per bit on the bus, minus one
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* @param prescale : The factor by which the Prescaler divides the SSP peripheral clock PCLK
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* @return Nothing
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* The bit frequency is PCLK / (prescale x[clk_rate+1])
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*/
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void IP_SSP_Set_ClockRate(IP_SSP_001_Type *pSSP, uint32_t clk_rate, uint32_t prescale);
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/**
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* @brief Set up the SSP frame format
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* @param pSSP : The base of SSP peripheral on the chip
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* @param bits : The number of bits transferred in each frame, should be SSP_BITS_4 to SSP_BITS_16
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* @param frameFormat : Frame format, should be :
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* - SSP_FRAMEFORMAT_SPI
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* - SSP_FRAMEFORMAT_TI
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* - SSP_FRAMEFORMAT_MICROWIRE
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* @param clockFormat : Select Clock polarity and Clock phase, should be :
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* - SSP_CLOCK_CPHA0_CPOL0
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* - SSP_CLOCK_CPHA0_CPOL1
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* - SSP_CLOCK_CPHA1_CPOL0
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* - SSP_CLOCK_CPHA1_CPOL1
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* @return Nothing
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* Note: The clockFormat is only used in SPI mode
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*/
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void IP_SSP_Set_Format(IP_SSP_001_Type *pSSP, uint32_t bits, uint32_t frameFormat, uint32_t clockFormat);
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/**
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* @brief Set the SSP working as master or slave mode
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* @param pSSP : The base of SSP peripheral on the chip
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* @param mode : Operating mode, should be
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* - SSP_MODE_MASTER
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* - SSP_MODE_SLAVE
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* @return Nothing
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*/
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void IP_SSP_Set_Mode(IP_SSP_001_Type *pSSP, uint32_t mode);
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/**
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* @brief Enable/Disable DMA for SSP
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* @param pSSP : The base of SSP peripheral on the chip
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* @param ssp_dma_t : DMA set up for transmit/receive SSP, should be
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* - SSP_DMA_RX
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* - SSP_DMA_TX
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* @param NewState : New state, ENABLE or DISABLE
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* @return Nothing
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*/
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void IP_SSP_DMA_Cmd(IP_SSP_001_Type *pSSP, SSP_DMA_Type ssp_dma_t, FunctionalState NewState);
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/**
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* @}
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*/
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#ifdef __cplusplus
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}
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#endif
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#endif /* __SSP_001_H_ */
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