rt-thread-official/bsp/tm4c129x-dk/context_rvds.lst

552 lines
22 KiB
Plaintext

ARM Macro Assembler Page 1
1 00000000 ;/*
2 00000000 ; * File : context_rvds.S
3 00000000 ; * This file is part of RT-Thread RTOS
4 00000000 ; * COPYRIGHT (C) 2009, RT-Thread Development Team
5 00000000 ; *
6 00000000 ; * The license and distribution terms for this file may
be
7 00000000 ; * found in the file LICENSE in this distribution or at
8 00000000 ; * http://www.rt-thread.org/license/LICENSE
9 00000000 ; *
10 00000000 ; * Change Logs:
11 00000000 ; * Date Author Notes
12 00000000 ; * 2009-01-17 Bernard first version.
13 00000000 ; * 2012-01-01 aozima support context switch l
oad/store FPU register.
14 00000000 ; * 2013-06-18 aozima add restore MSP feature.
15 00000000 ; * 2013-06-23 aozima support lazy stack optim
ized.
16 00000000 ; */
17 00000000
18 00000000 ;/**
19 00000000 ; * @addtogroup cortex-m4
20 00000000 ; */
21 00000000 ;/*@{*/
22 00000000
23 00000000 E000ED08
SCB_VTOR
EQU 0xE000ED08 ; Vector Table Offs
et Register
24 00000000 E000ED04
NVIC_INT_CTRL
EQU 0xE000ED04 ; interrupt control
state register
25 00000000 E000ED20
NVIC_SYSPRI2
EQU 0xE000ED20 ; system priority r
egister (2)
26 00000000 00FF0000
NVIC_PENDSV_PRI
EQU 0x00FF0000 ; PendSV priority v
alue (lowest)
27 00000000 10000000
NVIC_PENDSVSET
EQU 0x10000000 ; value to trigger
PendSV exception
28 00000000
29 00000000 AREA |.text|, CODE, READONLY, ALIGN=
2
30 00000000 THUMB
31 00000000 REQUIRE8
32 00000000 PRESERVE8
33 00000000
34 00000000 IMPORT rt_thread_switch_interrupt_flag
35 00000000 IMPORT rt_interrupt_from_thread
36 00000000 IMPORT rt_interrupt_to_thread
37 00000000
38 00000000 ;/*
ARM Macro Assembler Page 2
39 00000000 ; * rt_base_t rt_hw_interrupt_disable();
40 00000000 ; */
41 00000000 rt_hw_interrupt_disable
PROC
42 00000000 EXPORT rt_hw_interrupt_disable
43 00000000 F3EF 8010 MRS r0, PRIMASK
44 00000004 B672 CPSID I
45 00000006 4770 BX LR
46 00000008 ENDP
47 00000008
48 00000008 ;/*
49 00000008 ; * void rt_hw_interrupt_enable(rt_base_t level);
50 00000008 ; */
51 00000008 rt_hw_interrupt_enable
PROC
52 00000008 EXPORT rt_hw_interrupt_enable
53 00000008 F380 8810 MSR PRIMASK, r0
54 0000000C 4770 BX LR
55 0000000E ENDP
56 0000000E
57 0000000E ;/*
58 0000000E ; * void rt_hw_context_switch(rt_uint32 from, rt_uint32
to);
59 0000000E ; * r0 --> from
60 0000000E ; * r1 --> to
61 0000000E ; */
62 0000000E rt_hw_context_switch_interrupt
63 0000000E EXPORT rt_hw_context_switch_interrupt
64 0000000E rt_hw_context_switch
PROC
65 0000000E EXPORT rt_hw_context_switch
66 0000000E
67 0000000E ; set rt_thread_switch_interrupt_flag to 1
68 0000000E 4A3A LDR r2, =rt_thread_switch_interrupt
_flag
69 00000010 6813 LDR r3, [r2]
70 00000012 2B01 CMP r3, #1
71 00000014 D004 BEQ _reswitch
72 00000016 F04F 0301 MOV r3, #1
73 0000001A 6013 STR r3, [r2]
74 0000001C
75 0000001C 4A37 LDR r2, =rt_interrupt_from_thread ;
set rt_interrupt_f
rom_thread
76 0000001E 6010 STR r0, [r2]
77 00000020
78 00000020 _reswitch
79 00000020 4A37 LDR r2, =rt_interrupt_to_thread ; s
et rt_interrupt_to_
thread
80 00000022 6011 STR r1, [r2]
81 00000024
82 00000024 4837 LDR r0, =NVIC_INT_CTRL ; trigger th
e PendSV exception
(causes context swi
tch)
83 00000026 F04F 5180 LDR r1, =NVIC_PENDSVSET
84 0000002A 6001 STR r1, [r0]
85 0000002C 4770 BX LR
ARM Macro Assembler Page 3
86 0000002E ENDP
87 0000002E
88 0000002E ; r0 --> switch from thread stack
89 0000002E ; r1 --> switch to thread stack
90 0000002E ; psr, pc, lr, r12, r3, r2, r1, r0 are pushed into [from
] stack
91 0000002E PendSV_Handler
PROC
92 0000002E EXPORT PendSV_Handler
93 0000002E
94 0000002E ; disable interrupt to protect context switch
95 0000002E F3EF 8210 MRS r2, PRIMASK
96 00000032 B672 CPSID I
97 00000034
98 00000034 ; get rt_thread_switch_interrupt_flag
99 00000034 4830 LDR r0, =rt_thread_switch_interrupt
_flag
100 00000036 6801 LDR r1, [r0]
101 00000038 B351 CBZ r1, pendsv_exit ; pendsv alread
y handled
102 0000003A
103 0000003A ; clear rt_thread_switch_interrupt_flag to 0
104 0000003A F04F 0100 MOV r1, #0x00
105 0000003E 6001 STR r1, [r0]
106 00000040
107 00000040 482E LDR r0, =rt_interrupt_from_thread
108 00000042 6801 LDR r1, [r0]
109 00000044 B191 CBZ r1, switch_to_thread ; skip reg
ister save at the f
irst time
110 00000046
111 00000046 F3EF 8109 MRS r1, psp ; get from thread s
tack pointer
112 0000004A
113 0000004A IF {FPU} != "SoftVFP"
114 0000004A F01E 0F10 TST lr, #0x10 ; if(!EXC_RETURN[4]
)
115 0000004E BF08 ED21
8B10 VSTMFDEQ r1!, {d8 - d15} ; push FPU regi
ster s16~s31
116 00000054 ENDIF
117 00000054
118 00000054 E921 0FF0 STMFD r1!, {r4 - r11} ; push r4 - r11
register
119 00000058
120 00000058 IF {FPU} != "SoftVFP"
121 00000058 F04F 0400 MOV r4, #0x00 ; flag = 0
122 0000005C
123 0000005C F01E 0F10 TST lr, #0x10 ; if(!EXC_RETURN[4]
)
124 00000060 BF08 2401 MOVEQ r4, #0x01 ; flag = 1
125 00000064
126 00000064 F841 4D04 STMFD r1!, {r4} ; push flag
127 00000068 ENDIF
128 00000068
129 00000068 6800 LDR r0, [r0]
130 0000006A 6001 STR r1, [r0] ; update from threa
d stack pointer
131 0000006C
ARM Macro Assembler Page 4
132 0000006C switch_to_thread
133 0000006C 4924 LDR r1, =rt_interrupt_to_thread
134 0000006E 6809 LDR r1, [r1]
135 00000070 6809 LDR r1, [r1] ; load thread stack
pointer
136 00000072
137 00000072 IF {FPU} != "SoftVFP"
138 00000072 C908 LDMFD r1!, {r3} ; pop flag
139 00000074 ENDIF
140 00000074
141 00000074 E8B1 0FF0 LDMFD r1!, {r4 - r11} ; pop r4 - r11
register
142 00000078
143 00000078 IF {FPU} != "SoftVFP"
144 00000078 2B00 CMP r3, #0 ; if(flag_r3 != 0)
145 0000007A BF18 ECB1
8B10 VLDMFDNE r1!, {d8 - d15} ; pop FPU regis
ter s16~s31
146 00000080 ENDIF
147 00000080
148 00000080 F381 8809 MSR psp, r1 ; update stack poin
ter
149 00000084
150 00000084 IF {FPU} != "SoftVFP"
151 00000084 F04E 0E10 ORR lr, lr, #0x10 ; lr |= (1 << 4)
, clean FPCA.
152 00000088 2B00 CMP r3, #0 ; if(flag_r3 != 0)
153 0000008A BF18 F02E
0E10 BICNE lr, lr, #0x10 ; lr &= ~(1 << 4)
, set FPCA.
154 00000090 ENDIF
155 00000090
156 00000090 pendsv_exit
157 00000090 ; restore interrupt
158 00000090 F382 8810 MSR PRIMASK, r2
159 00000094
160 00000094 F04E 0E04 ORR lr, lr, #0x04
161 00000098 4770 BX lr
162 0000009A ENDP
163 0000009A
164 0000009A ;/*
165 0000009A ; * void rt_hw_context_switch_to(rt_uint32 to);
166 0000009A ; * r0 --> to
167 0000009A ; * this fucntion is used to perform the first thread sw
itch
168 0000009A ; */
169 0000009A rt_hw_context_switch_to
PROC
170 0000009A EXPORT rt_hw_context_switch_to
171 0000009A ; set to thread
172 0000009A 4919 LDR r1, =rt_interrupt_to_thread
173 0000009C 6008 STR r0, [r1]
174 0000009E
175 0000009E IF {FPU} != "SoftVFP"
176 0000009E ; CLEAR CONTROL.FPCA
177 0000009E F3EF 8214 MRS r2, CONTROL ; read
178 000000A2 F022 0204 BIC r2, #0x04 ; modify
179 000000A6 F382 8814 MSR CONTROL, r2 ; write-back
180 000000AA ENDIF
ARM Macro Assembler Page 5
181 000000AA
182 000000AA ; set from thread to 0
183 000000AA 4914 LDR r1, =rt_interrupt_from_thread
184 000000AC F04F 0000 MOV r0, #0x0
185 000000B0 6008 STR r0, [r1]
186 000000B2
187 000000B2 ; set interrupt flag to 1
188 000000B2 4911 LDR r1, =rt_thread_switch_interrupt
_flag
189 000000B4 F04F 0001 MOV r0, #1
190 000000B8 6008 STR r0, [r1]
191 000000BA
192 000000BA ; set the PendSV exception priority
193 000000BA 4813 LDR r0, =NVIC_SYSPRI2
194 000000BC F44F 017F LDR r1, =NVIC_PENDSV_PRI
195 000000C0 F8D0 2000 LDR.W r2, [r0,#0x00] ; read
196 000000C4 EA41 0102 ORR r1,r1,r2 ; modify
197 000000C8 6001 STR r1, [r0] ; write-back
198 000000CA
199 000000CA ; trigger the PendSV exception (causes context switch)
200 000000CA 480E LDR r0, =NVIC_INT_CTRL
201 000000CC F04F 5180 LDR r1, =NVIC_PENDSVSET
202 000000D0 6001 STR r1, [r0]
203 000000D2
204 000000D2 ; restore MSP
205 000000D2 480E LDR r0, =SCB_VTOR
206 000000D4 6800 LDR r0, [r0]
207 000000D6 6800 LDR r0, [r0]
208 000000D8 F380 8808 MSR msp, r0
209 000000DC
210 000000DC ; enable interrupts at processor level
211 000000DC B661 CPSIE F
212 000000DE B662 CPSIE I
213 000000E0
214 000000E0 ; never reach here!
215 000000E0 ENDP
216 000000E0
217 000000E0 ; compatible with old version
218 000000E0 rt_hw_interrupt_thread_switch
PROC
219 000000E0 EXPORT rt_hw_interrupt_thread_switch
220 000000E0 4770 BX lr
221 000000E2 ENDP
222 000000E2
223 000000E2 IMPORT rt_hw_hard_fault_exception
224 000000E2 EXPORT HardFault_Handler
225 000000E2 HardFault_Handler
PROC
226 000000E2
227 000000E2 ; get current context
228 000000E2 F3EF 8009 MRS r0, psp ; get fault thread
stack pointer
229 000000E6 B500 PUSH {lr}
230 000000E8 F7FF FFFE BL rt_hw_hard_fault_exception
231 000000EC F85D EB04 POP {lr}
232 000000F0
233 000000F0 F04E 0E04 ORR lr, lr, #0x04
234 000000F4 4770 BX lr
235 000000F6 ENDP
ARM Macro Assembler Page 6
236 000000F6
237 000000F6 00 00 ALIGN 4
238 000000F8
239 000000F8 END
00000000
00000000
00000000
E000ED04
E000ED20
E000ED08
Command Line: --debug --xref --diag_suppress=9931 --cpu=Cortex-M4.fp --apcs=int
erwork --depend=.\build\context_rvds.d -o.\build\context_rvds.o -IC:\Users\zylw
w\Documents\Study\CodeHub\rt-thread\bsp\tm4c129x-dk\RTE -IC:\Software\Keil\ARM\
PACK\Keil\TM4C_DFP\1.1.0\Device\Include\TM4C129 -IC:\Software\Keil\ARM\CMSIS\In
clude --predefine="__UVISION_VERSION SETA 521" --predefine="TM4C129XNCZAD SETA
1" --list=.\context_rvds.lst ../../libcpu/arm/cortex-m4/context_rvds.S
ARM Macro Assembler Page 1 Alphabetic symbol ordering
Relocatable symbols
.text 00000000
Symbol: .text
Definitions
At line 29 in file ../../libcpu/arm/cortex-m4/context_rvds.S
Uses
None
Comment: .text unused
HardFault_Handler 000000E2
Symbol: HardFault_Handler
Definitions
At line 225 in file ../../libcpu/arm/cortex-m4/context_rvds.S
Uses
At line 224 in file ../../libcpu/arm/cortex-m4/context_rvds.S
Comment: HardFault_Handler used once
PendSV_Handler 0000002E
Symbol: PendSV_Handler
Definitions
At line 91 in file ../../libcpu/arm/cortex-m4/context_rvds.S
Uses
At line 92 in file ../../libcpu/arm/cortex-m4/context_rvds.S
Comment: PendSV_Handler used once
_reswitch 00000020
Symbol: _reswitch
Definitions
At line 78 in file ../../libcpu/arm/cortex-m4/context_rvds.S
Uses
At line 71 in file ../../libcpu/arm/cortex-m4/context_rvds.S
Comment: _reswitch used once
pendsv_exit 00000090
Symbol: pendsv_exit
Definitions
At line 156 in file ../../libcpu/arm/cortex-m4/context_rvds.S
Uses
At line 101 in file ../../libcpu/arm/cortex-m4/context_rvds.S
Comment: pendsv_exit used once
rt_hw_context_switch 0000000E
Symbol: rt_hw_context_switch
Definitions
At line 64 in file ../../libcpu/arm/cortex-m4/context_rvds.S
Uses
At line 65 in file ../../libcpu/arm/cortex-m4/context_rvds.S
Comment: rt_hw_context_switch used once
rt_hw_context_switch_interrupt 0000000E
Symbol: rt_hw_context_switch_interrupt
Definitions
At line 62 in file ../../libcpu/arm/cortex-m4/context_rvds.S
Uses
At line 63 in file ../../libcpu/arm/cortex-m4/context_rvds.S
Comment: rt_hw_context_switch_interrupt used once
rt_hw_context_switch_to 0000009A
Symbol: rt_hw_context_switch_to
ARM Macro Assembler Page 2 Alphabetic symbol ordering
Relocatable symbols
Definitions
At line 169 in file ../../libcpu/arm/cortex-m4/context_rvds.S
Uses
At line 170 in file ../../libcpu/arm/cortex-m4/context_rvds.S
Comment: rt_hw_context_switch_to used once
rt_hw_interrupt_disable 00000000
Symbol: rt_hw_interrupt_disable
Definitions
At line 41 in file ../../libcpu/arm/cortex-m4/context_rvds.S
Uses
At line 42 in file ../../libcpu/arm/cortex-m4/context_rvds.S
Comment: rt_hw_interrupt_disable used once
rt_hw_interrupt_enable 00000008
Symbol: rt_hw_interrupt_enable
Definitions
At line 51 in file ../../libcpu/arm/cortex-m4/context_rvds.S
Uses
At line 52 in file ../../libcpu/arm/cortex-m4/context_rvds.S
Comment: rt_hw_interrupt_enable used once
rt_hw_interrupt_thread_switch 000000E0
Symbol: rt_hw_interrupt_thread_switch
Definitions
At line 218 in file ../../libcpu/arm/cortex-m4/context_rvds.S
Uses
At line 219 in file ../../libcpu/arm/cortex-m4/context_rvds.S
Comment: rt_hw_interrupt_thread_switch used once
switch_to_thread 0000006C
Symbol: switch_to_thread
Definitions
At line 132 in file ../../libcpu/arm/cortex-m4/context_rvds.S
Uses
At line 109 in file ../../libcpu/arm/cortex-m4/context_rvds.S
Comment: switch_to_thread used once
12 symbols
ARM Macro Assembler Page 1 Alphabetic symbol ordering
Absolute symbols
NVIC_INT_CTRL E000ED04
Symbol: NVIC_INT_CTRL
Definitions
At line 24 in file ../../libcpu/arm/cortex-m4/context_rvds.S
Uses
At line 82 in file ../../libcpu/arm/cortex-m4/context_rvds.S
At line 200 in file ../../libcpu/arm/cortex-m4/context_rvds.S
NVIC_PENDSVSET 10000000
Symbol: NVIC_PENDSVSET
Definitions
At line 27 in file ../../libcpu/arm/cortex-m4/context_rvds.S
Uses
At line 83 in file ../../libcpu/arm/cortex-m4/context_rvds.S
At line 201 in file ../../libcpu/arm/cortex-m4/context_rvds.S
NVIC_PENDSV_PRI 00FF0000
Symbol: NVIC_PENDSV_PRI
Definitions
At line 26 in file ../../libcpu/arm/cortex-m4/context_rvds.S
Uses
At line 194 in file ../../libcpu/arm/cortex-m4/context_rvds.S
Comment: NVIC_PENDSV_PRI used once
NVIC_SYSPRI2 E000ED20
Symbol: NVIC_SYSPRI2
Definitions
At line 25 in file ../../libcpu/arm/cortex-m4/context_rvds.S
Uses
At line 193 in file ../../libcpu/arm/cortex-m4/context_rvds.S
Comment: NVIC_SYSPRI2 used once
SCB_VTOR E000ED08
Symbol: SCB_VTOR
Definitions
At line 23 in file ../../libcpu/arm/cortex-m4/context_rvds.S
Uses
At line 205 in file ../../libcpu/arm/cortex-m4/context_rvds.S
Comment: SCB_VTOR used once
5 symbols
ARM Macro Assembler Page 1 Alphabetic symbol ordering
External symbols
rt_hw_hard_fault_exception 00000000
Symbol: rt_hw_hard_fault_exception
Definitions
At line 223 in file ../../libcpu/arm/cortex-m4/context_rvds.S
Uses
At line 230 in file ../../libcpu/arm/cortex-m4/context_rvds.S
Comment: rt_hw_hard_fault_exception used once
rt_interrupt_from_thread 00000000
Symbol: rt_interrupt_from_thread
Definitions
At line 35 in file ../../libcpu/arm/cortex-m4/context_rvds.S
Uses
At line 75 in file ../../libcpu/arm/cortex-m4/context_rvds.S
At line 107 in file ../../libcpu/arm/cortex-m4/context_rvds.S
At line 183 in file ../../libcpu/arm/cortex-m4/context_rvds.S
rt_interrupt_to_thread 00000000
Symbol: rt_interrupt_to_thread
Definitions
At line 36 in file ../../libcpu/arm/cortex-m4/context_rvds.S
Uses
At line 79 in file ../../libcpu/arm/cortex-m4/context_rvds.S
At line 133 in file ../../libcpu/arm/cortex-m4/context_rvds.S
At line 172 in file ../../libcpu/arm/cortex-m4/context_rvds.S
rt_thread_switch_interrupt_flag 00000000
Symbol: rt_thread_switch_interrupt_flag
Definitions
At line 34 in file ../../libcpu/arm/cortex-m4/context_rvds.S
Uses
At line 68 in file ../../libcpu/arm/cortex-m4/context_rvds.S
At line 99 in file ../../libcpu/arm/cortex-m4/context_rvds.S
At line 188 in file ../../libcpu/arm/cortex-m4/context_rvds.S
4 symbols
356 symbols in table