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de4f237482
* Update Kconfig * Update trap_gcc.S * Update bsp/hifive1/drivers/SConscript Co-authored-by: Man, Jianting (Meco) <920369182@qq.com> * Update SConscript * [atomic]提交一份arm与risc-v架构下的常用原子操作函数 * 修改变量类型 * 更新rtatomic.h与atomic_port.c * 更新rt-thread\libcpu\arm\common\atomic_port.c * 更新include/rtatomic.h与libcpu/arm/common/SConscript * 更新include/rtatomic.h * 修正格式与Kconfig * 修正格式与文件结构 * 规范文件格式与文件重命名 * 添加测试用例与CI * 添加函数声明 * 修改virt64/SConscript 添加atomic_riscv.c * 1.规范代码风格 * 2.添加RISC-V64原子指令支持 解决在RV64下编译器将32-bit运算结果扩展为64-bit 导致判断错误 * 添加C11标准库原子操作测试 --------- Co-authored-by: Man, Jianting (Meco) <920369182@qq.com>
160 lines
4.9 KiB
C
160 lines
4.9 KiB
C
/*
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* Copyright (c) 2006-2023, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2023-03-14 WangShun first version
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*/
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#include <rtthread.h>
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rt_atomic_t rt_hw_atomic_exchange(volatile rt_atomic_t *ptr, rt_atomic_t val)
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{
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rt_atomic_t result;
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#if __riscv_xlen == 32
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asm volatile ("amoswap.w %0, %1, (%2)" : "=r"(result) : "r"(val), "r"(ptr) : "memory");
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#elif __riscv_xlen == 64
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asm volatile ("amoswap.d %0, %1, (%2)" : "=r"(result) : "r"(val), "r"(ptr) : "memory");
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#endif
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return result;
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}
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rt_atomic_t rt_hw_atomic_add(volatile rt_atomic_t *ptr, rt_atomic_t val)
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{
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rt_atomic_t result;
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#if __riscv_xlen == 32
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asm volatile ("amoadd.w %0, %1, (%2)" : "=r"(result) : "r"(val), "r"(ptr) : "memory");
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#elif __riscv_xlen == 64
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asm volatile ("amoadd.d %0, %1, (%2)" : "=r"(result) : "r"(val), "r"(ptr) : "memory");
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#endif
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return result;
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}
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rt_atomic_t rt_hw_atomic_sub(volatile rt_atomic_t *ptr, rt_atomic_t val)
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{
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rt_atomic_t result;
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val = -val;
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#if __riscv_xlen == 32
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asm volatile ("amoadd.w %0, %1, (%2)" : "=r"(result) : "r"(val), "r"(ptr) : "memory");
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#elif __riscv_xlen == 64
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asm volatile ("amoadd.d %0, %1, (%2)" : "=r"(result) : "r"(val), "r"(ptr) : "memory");
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#endif
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return result;
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}
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rt_atomic_t rt_hw_atomic_xor(volatile rt_atomic_t *ptr, rt_atomic_t val)
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{
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rt_atomic_t result;
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#if __riscv_xlen == 32
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asm volatile ("amoxor.w %0, %1, (%2)" : "=r"(result) : "r"(val), "r"(ptr) : "memory");
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#elif __riscv_xlen == 64
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asm volatile ("amoxor.d %0, %1, (%2)" : "=r"(result) : "r"(val), "r"(ptr) : "memory");
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#endif
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return result;
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}
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rt_atomic_t rt_hw_atomic_and(volatile rt_atomic_t *ptr, rt_atomic_t val)
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{
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rt_atomic_t result;
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#if __riscv_xlen == 32
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asm volatile ("amoand.w %0, %1, (%2)" : "=r"(result) : "r"(val), "r"(ptr) : "memory");
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#elif __riscv_xlen == 64
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asm volatile ("amoand.d %0, %1, (%2)" : "=r"(result) : "r"(val), "r"(ptr) : "memory");
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#endif
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return result;
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}
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rt_atomic_t rt_hw_atomic_or(volatile rt_atomic_t *ptr, rt_atomic_t val)
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{
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rt_atomic_t result;
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#if __riscv_xlen == 32
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asm volatile ("amoor.w %0, %1, (%2)" : "=r"(result) : "r"(val), "r"(ptr) : "memory");
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#elif __riscv_xlen == 64
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asm volatile ("amoor.d %0, %1, (%2)" : "=r"(result) : "r"(val), "r"(ptr) : "memory");
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#endif
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return result;
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}
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rt_atomic_t rt_hw_atomic_load(volatile rt_atomic_t *ptr)
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{
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rt_atomic_t result;
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#if __riscv_xlen == 32
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asm volatile ("amoxor.w %0, x0, (%1)" : "=r"(result) : "r"(ptr) : "memory");
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#elif __riscv_xlen == 64
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asm volatile ("amoxor.d %0, x0, (%1)" : "=r"(result) : "r"(ptr) : "memory");
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#endif
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return result;
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}
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void rt_hw_atomic_store(volatile rt_atomic_t *ptr, rt_atomic_t val)
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{
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rt_atomic_t result;
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#if __riscv_xlen == 32
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asm volatile ("amoswap.w %0, %1, (%2)" : "=r"(result) : "r"(val), "r"(ptr) : "memory");
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#elif __riscv_xlen == 64
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asm volatile ("amoswap.d %0, %1, (%2)" : "=r"(result) : "r"(val), "r"(ptr) : "memory");
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#endif
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}
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rt_atomic_t rt_hw_atomic_flag_test_and_set(volatile rt_atomic_t *ptr)
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{
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rt_atomic_t result;
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rt_atomic_t temp = 1;
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#if __riscv_xlen == 32
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asm volatile ("amoor.w %0, %1, (%2)" : "=r"(result) : "r"(temp), "r"(ptr) : "memory");
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#elif __riscv_xlen == 64
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asm volatile ("amoor.d %0, %1, (%2)" : "=r"(result) : "r"(temp), "r"(ptr) : "memory");
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#endif
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return result;
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}
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void rt_hw_atomic_flag_clear(volatile rt_atomic_t *ptr)
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{
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rt_atomic_t result;
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#if __riscv_xlen == 32
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asm volatile ("amoand.w %0, x0, (%1)" : "=r"(result) :"r"(ptr) : "memory");
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#elif __riscv_xlen == 64
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asm volatile ("amoand.d %0, x0, (%1)" : "=r"(result) :"r"(ptr) : "memory");
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#endif
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}
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rt_atomic_t rt_hw_atomic_compare_exchange_strong(volatile rt_atomic_t *ptr, rt_atomic_t *old, rt_atomic_t new)
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{
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rt_atomic_t tmp = *old;
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rt_atomic_t result;
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#if __riscv_xlen == 32
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asm volatile(
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" fence iorw, ow\n"
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"1: lr.w.aq %[result], (%[ptr])\n"
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" bne %[result], %[tmp], 2f\n"
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" sc.w.rl %[tmp], %[new], (%[ptr])\n"
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" bnez %[tmp], 1b\n"
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" li %[result], 1\n"
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" j 3f\n"
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" 2:sw %[result], (%[old])\n"
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" li %[result], 0\n"
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" 3:\n"
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: [result]"+r" (result), [tmp]"+r" (tmp), [ptr]"+r" (ptr)
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: [new]"r" (new), [old]"r"(old)
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: "memory");
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#elif __riscv_xlen == 64
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asm volatile(
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" fence iorw, ow\n"
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"1: lr.d.aq %[result], (%[ptr])\n"
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" bne %[result], %[tmp], 2f\n"
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" sc.d.rl %[tmp], %[new], (%[ptr])\n"
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" bnez %[tmp], 1b\n"
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" li %[result], 1\n"
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" j 3f\n"
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" 2:sd %[result], (%[old])\n"
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" li %[result], 0\n"
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" 3:\n"
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: [result]"+r" (result), [tmp]"+r" (tmp), [ptr]"+r" (ptr)
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: [new]"r" (new), [old]"r"(old)
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: "memory");
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#endif
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return result;
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}
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