71 lines
3.5 KiB
C
71 lines
3.5 KiB
C
/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2021-01-30 lizhirui first version
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* 2021-11-18 JasonHu add fpu member
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* 2022-10-22 Shell Support kernel mode RVV
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*/
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#ifndef __STACK_H__
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#define __STACK_H__
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#include "stackframe.h"
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#include <rtthread.h>
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typedef struct rt_hw_switch_frame
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{
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uint64_t regs[RT_HW_SWITCH_CONTEXT_SIZE];
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} *rt_hw_switch_frame_t;
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struct rt_hw_stack_frame
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{
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rt_ubase_t epc; /* epc - epc - program counter */
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rt_ubase_t ra; /* x1 - ra - return address for jumps */
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rt_ubase_t sstatus; /* - supervisor status register */
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rt_ubase_t gp; /* x3 - gp - global pointer */
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rt_ubase_t tp; /* x4 - tp - thread pointer */
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rt_ubase_t t0; /* x5 - t0 - temporary register 0 */
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rt_ubase_t t1; /* x6 - t1 - temporary register 1 */
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rt_ubase_t t2; /* x7 - t2 - temporary register 2 */
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rt_ubase_t s0_fp; /* x8 - s0/fp - saved register 0 or frame pointer */
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rt_ubase_t s1; /* x9 - s1 - saved register 1 */
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rt_ubase_t a0; /* x10 - a0 - return value or function argument 0 */
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rt_ubase_t a1; /* x11 - a1 - return value or function argument 1 */
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rt_ubase_t a2; /* x12 - a2 - function argument 2 */
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rt_ubase_t a3; /* x13 - a3 - function argument 3 */
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rt_ubase_t a4; /* x14 - a4 - function argument 4 */
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rt_ubase_t a5; /* x15 - a5 - function argument 5 */
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rt_ubase_t a6; /* x16 - a6 - function argument 6 */
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rt_ubase_t a7; /* x17 - s7 - function argument 7 */
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rt_ubase_t s2; /* x18 - s2 - saved register 2 */
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rt_ubase_t s3; /* x19 - s3 - saved register 3 */
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rt_ubase_t s4; /* x20 - s4 - saved register 4 */
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rt_ubase_t s5; /* x21 - s5 - saved register 5 */
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rt_ubase_t s6; /* x22 - s6 - saved register 6 */
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rt_ubase_t s7; /* x23 - s7 - saved register 7 */
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rt_ubase_t s8; /* x24 - s8 - saved register 8 */
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rt_ubase_t s9; /* x25 - s9 - saved register 9 */
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rt_ubase_t s10; /* x26 - s10 - saved register 10 */
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rt_ubase_t s11; /* x27 - s11 - saved register 11 */
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rt_ubase_t t3; /* x28 - t3 - temporary register 3 */
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rt_ubase_t t4; /* x29 - t4 - temporary register 4 */
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rt_ubase_t t5; /* x30 - t5 - temporary register 5 */
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rt_ubase_t t6; /* x31 - t6 - temporary register 6 */
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rt_ubase_t user_sp_exc_stack; /* sscratch - user mode sp/exception stack */
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rt_ubase_t __padding; /* align to 16bytes */
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#ifdef ARCH_RISCV_FPU
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rt_ubase_t f[CTX_FPU_REG_NR]; /* f0~f31 */
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#endif /* ARCH_RISCV_FPU */
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#ifdef ARCH_RISCV_VECTOR
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rt_ubase_t v[CTX_VECTOR_REG_NR];
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#endif /* ARCH_RISCV_VECTOR */
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};
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#endif
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