298 lines
9.5 KiB
C
298 lines
9.5 KiB
C
/**
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******************************************************************************
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* @brief USART header file of the firmware library.
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******************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef __GD32F10X_USART_H
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#define __GD32F10X_USART_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Includes ------------------------------------------------------------------*/
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#include "gd32f10x.h"
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/** @addtogroup GD32F10x_Firmware
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* @{
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*/
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/** @addtogroup USART
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* @{
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*/
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/** @defgroup USART_Exported_Types
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* @{
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*/
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/**
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* @brief USART Initial Parameters
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*/
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typedef struct {
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uint32_t USART_BRR; /*!< the USART communication baud rate configuration */
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uint16_t USART_WL; /*!< Set by USART_CTLR1_WL Word length 0: 8 Data bits,
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1: 9 Data bits */
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uint16_t USART_STBits; /*!< Stop bits configuration */
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uint16_t USART_Parity; /*!< Set by USART_CTLR1_PCEN */
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uint16_t USART_RxorTx; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled. */
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uint16_t USART_HardwareFlowControl; /*!< Specifies wether the hardware flow control mode is enabled
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or disabled.This parameter can be a value of @ref USART_Hardware_Flow_Control */
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} USART_InitPara;
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/**
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* @brief USART Clock Init Structure definition
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*/
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typedef struct {
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uint16_t USART_CKEN; /*!< USART clock enabled this parameter can be a value of @ref USART_CKEN */
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uint16_t USART_CPL; /*!< Clock polarity of Steady state this parameter can be a value of @ref USART_Clock_Polarity */
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uint16_t USART_CPH; /*!< Clock phase this parameter can be a value of @ref USART_Clock_Phase */
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uint16_t USART_LBCP; /*!< Last bit clock pulse this parameter can be a value of @ref USART_Last_Bit */
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} USART_ClockInitPara;
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/**
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* @}
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*/
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/** @defgroup USART_Exported_Constants
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* @{
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*/
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/** @defgroup USART_WL
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* @{
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*/
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#define USART_WL_8B ((uint16_t)0x0000)
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#define USART_WL_9B USART_CTLR1_WL
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/**
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* @}
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*/
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/** @defgroup USART_STBits
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* @{
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*/
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#define USART_STBITS_1 ((uint16_t)0x0000)
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#define USART_STBITS_0_5 ((uint16_t)0x1000)
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#define USART_STBITS_2 USART_CTLR2_STB_1
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#define USART_STBITS_1_5 (USART_CTLR2_STB_0 | USART_CTLR2_STB_1)
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/**
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* @}
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*/
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/** @defgroup USART_Parity
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* @{
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*/
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#define USART_PARITY_RESET ((uint16_t)0x0000)
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#define USART_PARITY_SETEVEN USART_CTLR1_PCEN
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#define USART_PARITY_SETODD (USART_CTLR1_PCEN | USART_CTLR1_PM)
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/**
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* @}
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*/
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/** @defgroup USART_RxorTx
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* @{
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*/
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#define USART_RXORTX_RX USART_CTLR1_REN
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#define USART_RXORTX_TX USART_CTLR1_TEN
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/**
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* @}
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*/
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/** @defgroup USART_Hardware_Flow_Control
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* @{
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*/
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#define USART_HARDWAREFLOWCONTROL_NONE ((uint16_t)0x0000)
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#define USART_HARDWAREFLOWCONTROL_RTS USART_CTLR3_RTSEN
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#define USART_HARDWAREFLOWCONTROL_CTS USART_CTLR3_CTSEN
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#define USART_HARDWAREFLOWCONTROL_RTS_CTS (USART_CTLR3_RTSEN | USART_CTLR3_CTSEN)
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/**
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* @}
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*/
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/** @defgroup USART_CKEN
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* @{
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*/
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#define USART_CKEN_RESET ((uint16_t)0x0000)
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#define USART_CKEN_SET USART_CTLR2_CKEN
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/**
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* @}
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*/
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/** @defgroup USART_Clock_Polarity
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* @{
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*/
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#define USART_CPL_LOW ((uint16_t)0x0000)
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#define USART_CPL_HIGH USART_CTLR2_CPL
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/**
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* @}
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*/
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/** @defgroup USART_Clock_Phase
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* @{
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*/
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#define USART_CPH_1EDGE ((uint16_t)0x0000)
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#define USART_CPH_2EDGE USART_CTLR2_CPH
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/**
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* @}
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*/
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/** @defgroup USART_Last_Bit
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* @{
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*/
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#define USART_LBCP_DISABLE ((uint16_t)0x0000)
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#define USART_LBCP_ENABLE USART_CTLR2_LBCP
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/**
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* @}
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*/
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/** @defgroup USART_DMA_Requests
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* @{
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*/
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#define USART_DMAREQ_TX USART_CTLR3_DENT
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#define USART_DMAREQ_RX USART_CTLR3_DENR
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/**
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* @}
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*/
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/** @defgroup USART_Interrupt_definition
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* @brief USART Interrupt definition
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* USART_INT possible values
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* @{
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*/
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#define USART_INT_PE ((uint16_t)0x0028)
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#define USART_INT_TBE ((uint16_t)0x0727)
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#define USART_INT_TC ((uint16_t)0x0626)
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#define USART_INT_RBNE ((uint16_t)0x0525)
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#define USART_INT_IDLEF ((uint16_t)0x0424)
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#define USART_INT_LBDF ((uint16_t)0x0846)
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#define USART_INT_CTSF ((uint16_t)0x096A)
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#define USART_INT_ERIE ((uint16_t)0x0060)
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#define USART_INT_ORE ((uint16_t)0x0360)
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#define USART_INT_NE ((uint16_t)0x0260)
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#define USART_INT_FE ((uint16_t)0x0160)
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/**
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* @}
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*/
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/** @defgroup USART_MuteMode_WakeUp_methods
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* @{
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*/
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#define USART_WAKEUP_IDLELINE ((uint16_t)0x0000)
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#define USART_WAKEUP_ADDRESSMARK USART_CTLR1_WM
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/**
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* @}
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*/
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/** @defgroup USART_LIN_Break_Detection_Length
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* @{
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*/
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#define USART_LINBREAKDETECTLENGTH_10B ((uint16_t)0x0000)
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#define USART_LINBREAKDETECTLENGTH_11B USART_CTLR2_LBDL
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/**
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* @}
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*/
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/** @defgroup USART_IrDA_Low_Power
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* @{
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*/
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#define USART_IRDAMODE_LOWPOWER USART_CTLR3_IRLP
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#define USART_IRDAMODE_NORMAL ((uint16_t)0x0000)
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/**
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* @}
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*/
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/** @defgroup USART_Flags
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* @{
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*/
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#define USART_FLAG_CTSF ((uint16_t)0x0200)
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#define USART_FLAG_LBDF ((uint16_t)0x0100)
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#define USART_FLAG_TBE ((uint16_t)0x0080)
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#define USART_FLAG_TC ((uint16_t)0x0040)
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#define USART_FLAG_RBNE ((uint16_t)0x0020)
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#define USART_FLAG_IDLEF ((uint16_t)0x0010)
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#define USART_FLAG_ORE ((uint16_t)0x0008)
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#define USART_FLAG_NE ((uint16_t)0x0004)
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#define USART_FLAG_FE ((uint16_t)0x0002)
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#define USART_FLAG_PE ((uint16_t)0x0001)
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/**
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* @}
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*/
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/**
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* @}
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*/
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/** @defgroup USART_Exported_Functions
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* @{
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*/
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void USART_DeInit(USART_TypeDef *USARTx);
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void USART_Init(USART_TypeDef *USARTx, USART_InitPara *USART_InitParaStruct);
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void USART_ParaInit(USART_InitPara *USART_InitParaStruct);
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void USART_ClockInit(USART_TypeDef *USARTx, USART_ClockInitPara *USART_ClockInitStruct);
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void USART_ClockStructInit(USART_ClockInitPara *USART_ClockInitParaStruct);
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void USART_Enable(USART_TypeDef *USARTx, TypeState NewValue);
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void USART_HalfDuplex_Enable(USART_TypeDef *USARTx, TypeState NewValue);
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void USART_SetPrescaler(USART_TypeDef *USARTx, uint8_t USART_Prescaler);
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void USART_DataSend(USART_TypeDef *USARTx, uint16_t Data);
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uint16_t USART_DataReceive(USART_TypeDef *USARTx);
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void USART_Address(USART_TypeDef *USARTx, uint8_t USART_Address);
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void USART_MuteMode_Enable(USART_TypeDef *USARTx, TypeState NewState);
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void USART_MuteModeWakeUp_Set(USART_TypeDef *USARTx, uint16_t USART_WakeUp);
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void USART_SetLINBDLength(USART_TypeDef *USARTx, uint16_t USART_LINBreakDetectLength);
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void USART_LIN_Enable(USART_TypeDef *USARTx, TypeState NewValue);
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void USART_GuardTime_Set(USART_TypeDef *USARTx, uint8_t USART_GuardTime);
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void USART_SmartCard_Enable(USART_TypeDef *USARTx, TypeState NewValue);
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void USART_SmartCardNACK_Enable(USART_TypeDef *USARTx, TypeState NewValue);
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void USART_IrDA_Set(USART_TypeDef *USARTx, uint16_t USART_IrDAMode);
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void USART_IrDA_Enable(USART_TypeDef *USARTx, TypeState NewValue);
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void USART_DMA_Enable(USART_TypeDef *USARTx, uint16_t USART_DMAEnable, TypeState NewValue);
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void USART_INT_Set(USART_TypeDef *USARTx, uint16_t USART_INT, TypeState NewValue);
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TypeState USART_GetBitState(USART_TypeDef *USARTx, uint16_t USART_FLAG);
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void USART_ClearBitState(USART_TypeDef *USARTx, uint16_t USART_FLAG);
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TypeState USART_GetIntBitState(USART_TypeDef *USARTx, uint16_t USART_INT);
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void USART_ClearIntBitState(USART_TypeDef *USARTx, uint16_t USART_INT);
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void USART_SendBreak(USART_TypeDef *USARTx);
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#ifdef __cplusplus
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}
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#endif
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#endif /*__GD32F10X_USART_H */
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/**
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* @}
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*/
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/**
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* @}
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*/
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/**
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* @}
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*/
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