98 lines
3.6 KiB
C
98 lines
3.6 KiB
C
/*
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* Copyright (c) 2006-2024, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2023/06/25 flyingcys first version
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*/
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#ifndef __DRV_USART_H__
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#define __DRV_USART_H__
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#include <rtthread.h>
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#include "rtdevice.h"
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#include <rthw.h>
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#include "pinctrl.h"
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#include "mmio.h"
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#define UART_REG_SHIFT 0x2 /* Register Shift*/
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#define UART_INPUT_CLK 25000000
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#define UART0_BASE 0x04140000
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#define UART1_BASE 0x04150000
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#define UART2_BASE 0x04160000
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#define UART3_BASE 0x04170000
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#define UART4_BASE 0x041C0000
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#define UART0_IRQ (UART_IRQ_BASE + 0)
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#define UART1_IRQ (UART_IRQ_BASE + 1)
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#define UART2_IRQ (UART_IRQ_BASE + 2)
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#define UART3_IRQ (UART_IRQ_BASE + 3)
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#define UART4_IRQ (UART_IRQ_BASE + 4)
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/*
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* The Synopsys DesignWare 8250 has an extra feature whereby it detects if the
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* LCR is written whilst busy. If it is, then a busy detect interrupt is
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* raised, the LCR needs to be rewritten and the uart status register read.
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*/
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#define UART_RX 0 /* In: Receive buffer */
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#define UART_TX 0 /* Out: Transmit buffer */
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#define UART_DLL 0 /* Out: Divisor Latch Low */
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#define UART_DLM 1 /* Out: Divisor Latch High */
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#define UART_IER 1 /* Out: Interrupt Enable Register */
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#define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
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#define UART_SSR 0x22 /* In: Software Reset Register */
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#define UART_USR 0x1f /* UART Status Register */
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#define UART_IIR 2 /* In: Interrupt ID Register */
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#define UART_IIR_NO_INT 0x01 /* No interrupts pending */
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#define UART_IIR_BUSY 0x07 /* DesignWare APB Busy Detect */
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#define UART_IIR_RX_TIMEOUT 0x0c /* OMAP RX Timeout interrupt */
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#define UART_FCR 2 /* Out: FIFO Control Register */
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#define UART_FCR_FIFO_EN 0x01 /* Fifo enable */
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#define UART_FCR_RXSR 0x02 /* Receiver soft reset */
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#define UART_FCR_TXSR 0x04 /* Transmitter soft reset */
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#define UART_LCR 3 /* Out: Line Control Register */
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#define UART_LCR_WLS_MSK 0x03 /* character length select mask */
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#define UART_LCR_WLS_5 0x00 /* 5 bit character length */
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#define UART_LCR_WLS_6 0x01 /* 6 bit character length */
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#define UART_LCR_WLS_7 0x02 /* 7 bit character length */
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#define UART_LCR_WLS_8 0x03 /* 8 bit character length */
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#define UART_LCR_STB 0x04 /* # stop Bits, off=1, on=1.5 or 2) */
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#define UART_LCR_PEN 0x08 /* Parity eneble */
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#define UART_LCR_EPS 0x10 /* Even Parity Select */
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#define UART_LCR_STKP 0x20 /* Stick Parity */
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#define UART_LCR_SBRK 0x40 /* Set Break */
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#define UART_LCR_BKSE 0x80 /* Bank select enable */
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#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
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#define UART_MCR 4 /* Out: Modem Control Register */
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#define UART_MCR_DTR 0x01 /* DTR */
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#define UART_MCR_RTS 0x02 /* RTS */
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#define UART_LSR 5 /* In: Line Status Register */
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#define UART_LSR_BI 0x10 /* Break interrupt indicator */
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#define UART_LSR_DR 0x01 /* Receiver data ready */
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#define UART_LSR_TEMT 0x40 /* Transmitter empty */
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#define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
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#define UART_MCRVAL (UART_MCR_DTR | UART_MCR_RTS) /* RTS/DTR */
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/* Clear & enable FIFOs */
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#define UART_FCR_DEFVAL (UART_FCR_FIFO_EN | UART_FCR_RXSR | UART_FCR_TXSR)
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#define UART_LCR_8N1 0x03
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int rt_hw_uart_init(void);
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#endif /* __DRV_USART_H__ */
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