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ea6d73f140
1. Upgrade Cortex driver library (CMSIS -> CMSIS & Device): version 2.3.2 -> 3.0.1 & 3.0.0 - Remove "bsp/efm32/Libraries/CMSIS/Lib/ARM", "bsp/efm32/Libraries/CMSIS/Lib/G++" and "bsp/efm32/Libraries/CMSIS/SVD" to save space 2. Upgrade EFM32 driver libraries (efm32lib -> emlib): version 2.3.2 -> 3.0.0 - Remove "bsp/efm32/Libraries/Device/EnergyMicro/EFM32LG" and "bsp/efm32/Libraries/Device/EnergyMicro/EFM32TG" to save space 3. Upgrade EFM32GG_DK3750 development kit driver library: version 1.2.2 -> 2.0.1 4. Upgrade EFM32_Gxxx_DK development kit driver library: version 1.7.3 -> 2.0.1 5. Add energy management unit driver and test code 6. Modify linker script and related code to compatible with new version of libraries 7. Change EFM32 branch version number to 1.0 8. Add photo frame demo application git-svn-id: https://rt-thread.googlecode.com/svn/trunk@2122 bbd45198-f89e-11dd-88c7-29a3b14d5316
254 lines
9.4 KiB
C
254 lines
9.4 KiB
C
/**************************************************************************//**
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* @file
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* @brief EFM32GG_DK3750 board support package SPI API implementation
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* @author Energy Micro AS
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* @version 2.0.1
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******************************************************************************
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* @section License
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* <b>(C) Copyright 2012 Energy Micro AS, http://www.energymicro.com</b>
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*******************************************************************************
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*
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* Permission is granted to anyone to use this software for any purpose,
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* including commercial applications, and to alter it and redistribute it
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* freely, subject to the following restrictions:
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*
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* 1. The origin of this software must not be misrepresented; you must not
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* claim that you wrote the original software.
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* 2. Altered source versions must be plainly marked as such, and must not be
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* misrepresented as being the original software.
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* 3. This notice may not be removed or altered from any source distribution.
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* 4. The source and compiled code may only be used on Energy Micro "EFM32"
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* microcontrollers and "EFR4" radios.
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*
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* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Energy Micro AS has no
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* obligation to support this Software. Energy Micro AS is providing the
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* Software "AS IS", with no express or implied warranties of any kind,
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* including, but not limited to, any implied warranties of merchantability
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* or fitness for any particular purpose or warranties against infringement
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* of any proprietary rights of a third party.
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*
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* Energy Micro AS will not be liable for any consequential, incidental, or
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* special damages, or any other relief, or for any claim by any third party,
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* arising from your use of this Software.
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*
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*****************************************************************************/
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/***************************************************************************//**
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* @addtogroup BSP
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* @{
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******************************************************************************/
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#include "efm32.h"
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#include "em_gpio.h"
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#include "em_usart.h"
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#include "em_cmu.h"
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#include "dvk.h"
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#include "dvk_bcregisters.h"
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/* USART used for SPI access */
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#define USART_USED USART2 /**< USART used for BC register interface */
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#define USART_CLK cmuClock_USART2 /**< Clock for BC register USART */
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/* GPIO pins used, please refer to DVK user guide. */
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#define PORT_SPI_TX gpioPortC /**< SPI transmit GPIO port */
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#define PIN_SPI_TX 2 /**< SPI transmit GPIO pin */
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#define PORT_SPI_RX gpioPortC /**< SPI receive GPIO port */
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#define PIN_SPI_RX 3 /**< SPI receive GPIO pin */
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#define PORT_SPI_CLK gpioPortC /**< SPI clock port */
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#define PIN_SPI_CLK 4 /**< SPI clock pin */
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#define PORT_SPI_CS gpioPortC /**< SPI Chip Select port */
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#define PIN_SPI_CS 5 /**< SPI Chip Select pin */
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static volatile const uint16_t *lastAddr = 0; /**< Last register accessed */
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/**************************************************************************//**
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* @brief Initializes SPI interface for access to board controller
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* FPGA registers
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*****************************************************************************/
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static void SPI_BC_Init(void)
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{
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USART_InitSync_TypeDef bcinit = USART_INITSYNC_DEFAULT;
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/* Enable module clocks */
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CMU_ClockEnable(USART_CLK, true);
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/* Configure SPI pins */
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GPIO_PinModeSet(PORT_SPI_TX, PIN_SPI_TX, gpioModePushPull, 0);
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GPIO_PinModeSet(PORT_SPI_RX, PIN_SPI_RX, gpioModeInput, 0);
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GPIO_PinModeSet(PORT_SPI_CLK, PIN_SPI_CLK, gpioModePushPull, 0);
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/* Keep CS high to not activate slave */
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GPIO_PinModeSet(PORT_SPI_CS, PIN_SPI_CS, gpioModePushPull, 1);
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/* Configure to use SPI master with manual CS */
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/* For now, configure SPI for worst case 48MHz clock in order to work for all */
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/* configurations. */
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bcinit.refFreq = 48000000;
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bcinit.baudrate = 7000000;
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/* Initialize USART */
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USART_InitSync(USART_USED, &bcinit);
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/* Enable pins at default location */
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USART_USED->ROUTE = USART_ROUTE_TXPEN | USART_ROUTE_RXPEN | USART_ROUTE_CLKPEN;
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}
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/**************************************************************************//**
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* @brief Disables GPIO pins and USART from FPGA register access
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*****************************************************************************/
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static void SPI_BC_Disable(void)
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{
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/* Restore and disable USART */
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USART_Reset(USART_USED);
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GPIO_PinModeSet(PORT_SPI_TX, PIN_SPI_TX, gpioModeDisabled, 0);
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GPIO_PinModeSet(PORT_SPI_RX, PIN_SPI_RX, gpioModeDisabled, 0);
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GPIO_PinModeSet(PORT_SPI_CLK, PIN_SPI_CLK, gpioModeDisabled, 0);
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GPIO_PinModeSet(PORT_SPI_CS, PIN_SPI_CS, gpioModeDisabled, 0);
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/* Disable USART clock - we can't disable GPIO or HFPER as we don't know who else
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* might be using it */
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CMU_ClockEnable(USART_CLK, false);
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}
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/**************************************************************************//**
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* @brief Perform SPI Transfer
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* @param addr Register offset, starting at 0
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* @param rw 0 on write, 1 on read accesses
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* @param data 16-bit data to write into register/dummy data for reads
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* @return 16-bit data received from SPI access
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*****************************************************************************/
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static uint16_t SPI_BC_Access(uint8_t addr, uint8_t rw, uint16_t data)
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{
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uint16_t tmp;
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/* Enable CS */
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GPIO_PinOutClear(PORT_SPI_CS, PIN_SPI_CS);
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/* Write SPI address MSB */
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USART_Tx(USART_USED, (addr & 0x3) | rw << 3);
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/* Just ignore data read back */
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USART_Rx(USART_USED);
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/* Write SPI address LSB */
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USART_Tx(USART_USED, data & 0xFF);
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tmp = (uint16_t) USART_Rx(USART_USED);
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/* SPI data MSB */
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USART_Tx(USART_USED, data >> 8);
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tmp |= (uint16_t) USART_Rx(USART_USED) << 8;
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/* Disable CS */
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GPIO_PinOutSet(PORT_SPI_CS, PIN_SPI_CS);
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return tmp;
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}
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/**************************************************************************//**
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* @brief Performs SPI write to FPGA register
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* @param addr Address of register
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* @param data Data to write
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*****************************************************************************/
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static void SPI_BC_Write(uint8_t addr, uint16_t data)
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{
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SPI_BC_Access(addr, 0, data);
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}
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/**************************************************************************//**
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* @brief Performs SPI read from FPGA register
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* @param addr Address of register
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* @return 16-bit value of board controller register
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*****************************************************************************/
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static uint16_t SPI_BC_Read(uint8_t addr)
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{
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return SPI_BC_Access(addr, 1, 0);
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}
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/**************************************************************************//**
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* @brief Initializes DVK register access
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* @return true on success, false on failure
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*****************************************************************************/
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bool DVK_SPI_init(void)
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{
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uint16_t bcMagic;
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/* Enable HF and GPIO clocks */
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CMU_ClockEnable(cmuClock_HFPER, true);
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CMU_ClockEnable(cmuClock_GPIO, true);
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/* Configure SPI mode of operation */
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DVK_busControlMode(DVK_BusControl_SPI);
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SPI_BC_Init();
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/* Read "board control Magic" register to verify SPI is up and running */
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/* if not FPGA is configured to be in EBI mode */
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bcMagic = DVK_SPI_readRegister(&BC_REGISTER->MAGIC);
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if (bcMagic != BC_MAGIC_VALUE)
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{
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return false;
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}
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else
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{
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return true;
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}
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}
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/**************************************************************************//**
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* @brief Disable and free up resources used by SPI board control access
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*****************************************************************************/
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void DVK_SPI_disable(void)
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{
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SPI_BC_Disable();
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}
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/**************************************************************************//**
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* @brief Perform read from DVK board control register
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* @param[in] addr Address of register to read from
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* @return Value of board controller register
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*****************************************************************************/
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uint16_t DVK_SPI_readRegister(volatile uint16_t *addr)
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{
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uint16_t data;
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if (addr != lastAddr)
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{
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SPI_BC_Write(0x00, 0xFFFF & ((uint32_t) addr)); /*LSBs of address*/
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SPI_BC_Write(0x01, 0xFF & ((uint32_t) addr >> 16)); /*MSBs of address*/
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SPI_BC_Write(0x02, (0x0C000000 & (uint32_t) addr) >> 26); /*Chip select*/
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}
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/* Read twice; when register address has changed we need two SPI transfer
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* to clock out valid data through board controller FIFOs */
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data = SPI_BC_Read(0x03);
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data = SPI_BC_Read(0x03);
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lastAddr = addr;
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return data;
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}
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/**************************************************************************//**
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* @brief Perform write to DVK board control register
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* @param addr Address of register to write to
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* @param data 16-bit to write into register
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*****************************************************************************/
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void DVK_SPI_writeRegister(volatile uint16_t *addr, uint16_t data)
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{
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if (addr != lastAddr)
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{
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SPI_BC_Write(0x00, 0xFFFF & ((uint32_t) addr)); /*LSBs of address*/
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SPI_BC_Write(0x01, 0xFF & ((uint32_t) addr >> 16)); /*MSBs of address*/
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SPI_BC_Write(0x02, (0x0C000000 & (uint32_t) addr) >> 26); /*Chip select*/
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}
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SPI_BC_Write(0x03, data); /*Data*/
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lastAddr = addr;
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}
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/** @} (end group BSP) */
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