638 lines
16 KiB
C
638 lines
16 KiB
C
/**************************************************************************//**
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* @file core_cmFunc.h
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* @brief CMSIS Cortex-M Core Function Access Header File
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* @version V4.00
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* @date 28. August 2014
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*
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* @note
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*
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******************************************************************************/
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/* Copyright (c) 2009 - 2014 ARM LIMITED
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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- Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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- Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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- Neither the name of ARM nor the names of its contributors may be used
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to endorse or promote products derived from this software without
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specific prior written permission.
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*
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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POSSIBILITY OF SUCH DAMAGE.
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---------------------------------------------------------------------------*/
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#ifndef __CORE_CMFUNC_H
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#define __CORE_CMFUNC_H
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/* ########################### Core Function Access ########################### */
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/** \ingroup CMSIS_Core_FunctionInterface
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\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
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@{
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*/
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#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
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/* ARM armcc specific functions */
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#if (__ARMCC_VERSION < 400677)
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#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
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#endif
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/* intrinsic void __enable_irq(); */
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/* intrinsic void __disable_irq(); */
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/** \brief Get Control Register
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This function returns the content of the Control Register.
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\return Control Register value
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*/
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__STATIC_INLINE uint32_t __get_CONTROL(void)
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{
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register uint32_t __regControl __ASM("control");
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return(__regControl);
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}
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/** \brief Set Control Register
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This function writes the given value to the Control Register.
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\param [in] control Control Register value to set
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*/
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__STATIC_INLINE void __set_CONTROL(uint32_t control)
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{
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register uint32_t __regControl __ASM("control");
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__regControl = control;
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}
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/** \brief Get IPSR Register
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This function returns the content of the IPSR Register.
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\return IPSR Register value
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*/
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__STATIC_INLINE uint32_t __get_IPSR(void)
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{
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register uint32_t __regIPSR __ASM("ipsr");
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return(__regIPSR);
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}
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/** \brief Get APSR Register
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This function returns the content of the APSR Register.
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\return APSR Register value
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*/
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__STATIC_INLINE uint32_t __get_APSR(void)
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{
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register uint32_t __regAPSR __ASM("apsr");
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return(__regAPSR);
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}
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/** \brief Get xPSR Register
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This function returns the content of the xPSR Register.
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\return xPSR Register value
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*/
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__STATIC_INLINE uint32_t __get_xPSR(void)
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{
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register uint32_t __regXPSR __ASM("xpsr");
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return(__regXPSR);
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}
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/** \brief Get Process Stack Pointer
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This function returns the current value of the Process Stack Pointer (PSP).
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\return PSP Register value
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*/
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__STATIC_INLINE uint32_t __get_PSP(void)
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{
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register uint32_t __regProcessStackPointer __ASM("psp");
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return(__regProcessStackPointer);
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}
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/** \brief Set Process Stack Pointer
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This function assigns the given value to the Process Stack Pointer (PSP).
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\param [in] topOfProcStack Process Stack Pointer value to set
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*/
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__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
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{
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register uint32_t __regProcessStackPointer __ASM("psp");
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__regProcessStackPointer = topOfProcStack;
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}
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/** \brief Get Main Stack Pointer
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This function returns the current value of the Main Stack Pointer (MSP).
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\return MSP Register value
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*/
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__STATIC_INLINE uint32_t __get_MSP(void)
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{
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register uint32_t __regMainStackPointer __ASM("msp");
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return(__regMainStackPointer);
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}
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/** \brief Set Main Stack Pointer
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This function assigns the given value to the Main Stack Pointer (MSP).
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\param [in] topOfMainStack Main Stack Pointer value to set
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*/
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__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
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{
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register uint32_t __regMainStackPointer __ASM("msp");
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__regMainStackPointer = topOfMainStack;
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}
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/** \brief Get Priority Mask
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This function returns the current state of the priority mask bit from the Priority Mask Register.
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\return Priority Mask value
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*/
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__STATIC_INLINE uint32_t __get_PRIMASK(void)
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{
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register uint32_t __regPriMask __ASM("primask");
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return(__regPriMask);
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}
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/** \brief Set Priority Mask
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This function assigns the given value to the Priority Mask Register.
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\param [in] priMask Priority Mask
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*/
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__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
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{
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register uint32_t __regPriMask __ASM("primask");
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__regPriMask = (priMask);
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}
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#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
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/** \brief Enable FIQ
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This function enables FIQ interrupts by clearing the F-bit in the CPSR.
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Can only be executed in Privileged modes.
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*/
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#define __enable_fault_irq __enable_fiq
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/** \brief Disable FIQ
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This function disables FIQ interrupts by setting the F-bit in the CPSR.
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Can only be executed in Privileged modes.
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*/
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#define __disable_fault_irq __disable_fiq
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/** \brief Get Base Priority
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This function returns the current value of the Base Priority register.
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\return Base Priority register value
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*/
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__STATIC_INLINE uint32_t __get_BASEPRI(void)
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{
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register uint32_t __regBasePri __ASM("basepri");
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return(__regBasePri);
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}
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/** \brief Set Base Priority
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This function assigns the given value to the Base Priority register.
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\param [in] basePri Base Priority value to set
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*/
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__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
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{
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register uint32_t __regBasePri __ASM("basepri");
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__regBasePri = (basePri & 0xff);
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}
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/** \brief Get Fault Mask
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This function returns the current value of the Fault Mask register.
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\return Fault Mask register value
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*/
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__STATIC_INLINE uint32_t __get_FAULTMASK(void)
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{
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register uint32_t __regFaultMask __ASM("faultmask");
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return(__regFaultMask);
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}
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/** \brief Set Fault Mask
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This function assigns the given value to the Fault Mask register.
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\param [in] faultMask Fault Mask value to set
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*/
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__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
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{
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register uint32_t __regFaultMask __ASM("faultmask");
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__regFaultMask = (faultMask & (uint32_t)1);
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}
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#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
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#if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
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/** \brief Get FPSCR
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This function returns the current value of the Floating Point Status/Control register.
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\return Floating Point Status/Control register value
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*/
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__STATIC_INLINE uint32_t __get_FPSCR(void)
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{
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#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
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register uint32_t __regfpscr __ASM("fpscr");
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return(__regfpscr);
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#else
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return(0);
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#endif
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}
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/** \brief Set FPSCR
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This function assigns the given value to the Floating Point Status/Control register.
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\param [in] fpscr Floating Point Status/Control value to set
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*/
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__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
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{
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#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
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register uint32_t __regfpscr __ASM("fpscr");
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__regfpscr = (fpscr);
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#endif
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}
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#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
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#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
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/* GNU gcc specific functions */
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/** \brief Enable IRQ Interrupts
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This function enables IRQ interrupts by clearing the I-bit in the CPSR.
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Can only be executed in Privileged modes.
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*/
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__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
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{
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__ASM volatile ("cpsie i" : : : "memory");
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}
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/** \brief Disable IRQ Interrupts
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This function disables IRQ interrupts by setting the I-bit in the CPSR.
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Can only be executed in Privileged modes.
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*/
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__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
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{
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__ASM volatile ("cpsid i" : : : "memory");
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}
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/** \brief Get Control Register
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This function returns the content of the Control Register.
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\return Control Register value
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*/
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__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
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{
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uint32_t result;
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__ASM volatile ("MRS %0, control" : "=r" (result) );
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return(result);
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}
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/** \brief Set Control Register
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This function writes the given value to the Control Register.
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\param [in] control Control Register value to set
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*/
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__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
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{
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__ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
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}
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/** \brief Get IPSR Register
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This function returns the content of the IPSR Register.
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\return IPSR Register value
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*/
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__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
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{
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uint32_t result;
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__ASM volatile ("MRS %0, ipsr" : "=r" (result) );
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return(result);
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}
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/** \brief Get APSR Register
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This function returns the content of the APSR Register.
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\return APSR Register value
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*/
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__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
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{
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uint32_t result;
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__ASM volatile ("MRS %0, apsr" : "=r" (result) );
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return(result);
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}
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/** \brief Get xPSR Register
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This function returns the content of the xPSR Register.
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\return xPSR Register value
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*/
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__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
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{
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uint32_t result;
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__ASM volatile ("MRS %0, xpsr" : "=r" (result) );
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return(result);
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}
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/** \brief Get Process Stack Pointer
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This function returns the current value of the Process Stack Pointer (PSP).
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\return PSP Register value
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*/
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__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
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{
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register uint32_t result;
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__ASM volatile ("MRS %0, psp\n" : "=r" (result) );
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return(result);
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}
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/** \brief Set Process Stack Pointer
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This function assigns the given value to the Process Stack Pointer (PSP).
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\param [in] topOfProcStack Process Stack Pointer value to set
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*/
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__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
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{
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__ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
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}
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/** \brief Get Main Stack Pointer
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This function returns the current value of the Main Stack Pointer (MSP).
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\return MSP Register value
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*/
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__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
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{
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register uint32_t result;
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__ASM volatile ("MRS %0, msp\n" : "=r" (result) );
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return(result);
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}
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/** \brief Set Main Stack Pointer
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This function assigns the given value to the Main Stack Pointer (MSP).
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\param [in] topOfMainStack Main Stack Pointer value to set
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*/
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__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
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{
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__ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
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}
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/** \brief Get Priority Mask
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This function returns the current state of the priority mask bit from the Priority Mask Register.
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\return Priority Mask value
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*/
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__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
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{
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uint32_t result;
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__ASM volatile ("MRS %0, primask" : "=r" (result) );
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return(result);
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}
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/** \brief Set Priority Mask
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This function assigns the given value to the Priority Mask Register.
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\param [in] priMask Priority Mask
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*/
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__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
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{
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__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
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}
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#if (__CORTEX_M >= 0x03)
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/** \brief Enable FIQ
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This function enables FIQ interrupts by clearing the F-bit in the CPSR.
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Can only be executed in Privileged modes.
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*/
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__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
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{
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__ASM volatile ("cpsie f" : : : "memory");
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}
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/** \brief Disable FIQ
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This function disables FIQ interrupts by setting the F-bit in the CPSR.
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Can only be executed in Privileged modes.
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*/
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__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
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{
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__ASM volatile ("cpsid f" : : : "memory");
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}
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/** \brief Get Base Priority
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This function returns the current value of the Base Priority register.
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\return Base Priority register value
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*/
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__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
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{
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uint32_t result;
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__ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
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return(result);
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}
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/** \brief Set Base Priority
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This function assigns the given value to the Base Priority register.
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\param [in] basePri Base Priority value to set
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*/
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__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
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{
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__ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
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}
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/** \brief Get Fault Mask
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This function returns the current value of the Fault Mask register.
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\return Fault Mask register value
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*/
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__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
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{
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uint32_t result;
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__ASM volatile ("MRS %0, faultmask" : "=r" (result) );
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return(result);
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}
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/** \brief Set Fault Mask
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This function assigns the given value to the Fault Mask register.
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\param [in] faultMask Fault Mask value to set
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*/
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__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
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{
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__ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
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}
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#endif /* (__CORTEX_M >= 0x03) */
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#if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
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/** \brief Get FPSCR
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This function returns the current value of the Floating Point Status/Control register.
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\return Floating Point Status/Control register value
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*/
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__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
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{
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#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
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uint32_t result;
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/* Empty asm statement works as a scheduling barrier */
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__ASM volatile ("");
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__ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
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__ASM volatile ("");
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return(result);
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#else
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return(0);
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#endif
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}
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/** \brief Set FPSCR
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This function assigns the given value to the Floating Point Status/Control register.
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\param [in] fpscr Floating Point Status/Control value to set
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*/
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__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
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|
{
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#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
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/* Empty asm statement works as a scheduling barrier */
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|
__ASM volatile ("");
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__ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
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|
__ASM volatile ("");
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#endif
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}
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#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
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#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
|
|
/* IAR iccarm specific functions */
|
|
#include <cmsis_iar.h>
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|
|
|
|
|
#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
|
|
/* TI CCS specific functions */
|
|
#include <cmsis_ccs.h>
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|
|
|
|
|
#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
|
|
/* TASKING carm specific functions */
|
|
/*
|
|
* The CMSIS functions have been implemented as intrinsics in the compiler.
|
|
* Please use "carm -?i" to get an up to date list of all intrinsics,
|
|
* Including the CMSIS ones.
|
|
*/
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|
|
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|
|
#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
|
|
/* Cosmic specific functions */
|
|
#include <cmsis_csm.h>
|
|
|
|
#endif
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|
|
/*@} end of CMSIS_Core_RegAccFunctions */
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|
#endif /* __CORE_CMFUNC_H */
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