d724eed9fc
* [kernel][mem] Multiple instances of small memory allocation algorithm * [kernel][mem] Change small memory management algorithm memory header flag * [kernel][mem] Fix assertion problem * [kernel][slab] Multiple instances of slab memory management algorithm * [kernel][memheap] Remove rt_malloc/rt_free/rt_realloc and other related memory interfaces * [kernel][mem] Clean up memory space of small memory management objects * [kernel][kservice] Add memory application interface and thread protection interface * [kernel][kservice] Fix function return value problem * [kernel][memheap] Optimize memheaptrace print * [kernel][memheap] Support best mode * [kernel][memory] Remove semaphore lock * [kernel][memheap] Add locked flag * [kernel][memory] Support malloc memory in interrupt * [kernel][memheap] Add 'memheapcheck' cmd * [kernel][mem] Fix failure to request full memory * [kernel][memheap] Fix compilation warning * [kernel][mem] Fix mem realloc ASSERT * [examples][testcases] Add small mem testcase * [examples][mem_tc] Modify test memory size * [examples][testcases] Add slab memory management algorithm test case * [examples][testcases] fix small memory management algorithm test case * [kernel][memory] Adjusting memory allocation algorithm object definition and interface * [kernel][memory] Fix compilation warning * [examples][utest] Fix mem test case * [examples][utest] fix slab test case * [utest][testcases] Shorten test time * [kernel][memory] Formatting code * [examples][utest] Adjust test run time * [examples][utest] Formatting code * [bsp] update all rtconfig.h
STM32G070-Nucleo BSP Introduction
MCU: STM32G070RB @64MHz, 128KB FLASH, 36KB RAM
The STM32G070CB/KB/RB mainstream microcontrollers are based on high-performance Arm® Cortex®-M0+ 32-bit RISC core operating at up to 64 MHz frequency. Offering a high level of integration, they are suitable for a wide range of applications in consumer, industrial and appliance domains and ready for the Internet of Things (IoT) solutions.
The devices incorporate a memory protection unit (MPU), high-speed embedded memories (128 Kbytes of Flash program memory with read protection, write protection, and 36 Kbytes of SRAM), DMA and an extensive range of system functions, enhanced I/Os and peripherals. The devices offer standard communication interfaces (two I2Cs, two SPIs / one I2S, and four USARTs), one 12-bit ADC (2.5 MSps) with up to 19 channels, a low-power RTC, an advanced control PWM timer, five general-purpose 16-bit timers, two basic timers, two watchdog timers, and a SysTick timer. The devices operate within ambient temperatures from -40 to 85°C. They can operate with supply voltages from 2.0 V to 3.6 V. Optimized dynamic consumption combined with a comprehensive set of power-saving modes allows the design of low-power applications. VBAT direct battery input allows keeping RTC and backup registers powered. The devices come in packages with 32 to 64 pins.
KEY FEATURES
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Core: Arm® 32-bit Cortex®-M0+ CPU, frequency up to 64 MHz
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-40°C to 85°C operating temperature
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Memories
- 128 Kbytes of Flash memory with protection
- 36 Kbytes of SRAM (32 Kbytes with HW parity check)
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CRC calculation unit
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Reset and power management
- Voltage range: 2.0 V to 3.6 V
- Power-on/Power-down reset (POR/PDR)
- Low-power modes:Sleep, Stop, Standby
- VBAT supply for RTC and backup registers
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Clock management
- 4 to 48 MHz crystal oscillator
- 32 kHz crystal oscillator with calibration
- Internal 16 MHz RC with PLL option
- Internal 32 kHz RC oscillator (±5 %)
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Up to 59 fast I/Os
- All mappable on external interrupt vectors
- Multiple 5 V-tolerant I/Os
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7-channel DMA controller with flexible mapping
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12-bit, 0.4 µs ADC (up to 16 ext. channels)
- Up to 16-bit with hardware oversampling
- Conversion range: 0 to 3.6V
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11 timers: 16-bit for advanced motor control, five 16-bit general-purpose, two basic 16-bit, two watchdogs, SysTick timer
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Calendar RTC with alarm and periodic wakeup from Stop/Standby
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Communication interfaces
- Two I2C-bus interfaces supporting Fast-mode Plus (1 Mbit/s) with extra current sink, one supporting SMBus/PMBus and wakeup from Stop mode
- Four USARTs with master/slave synchronous SPI; two supporting ISO7816 interface, LIN, IrDA capability, auto baud rate detection and wakeup feature
- Two SPIs (32 Mbit/s) with 4- to 16-bit programmable bitframe, one multiplexed with I2S interface
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Development support: serial wire debug (SWD)
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All packages ECOPACK 2 compliant
Read more
| Documents | Description |
|---|---|
| STM32_Nucleo-64_BSP_Introduction | How to run RT-Thread on STM32 Nucleo-64 boards (Must-Read) |
| STM32G070RB ST Official Website | STM32G070RB datasheet and other resources |
Maintained By
Translated By
Meco Man @ RT-Thread Community