658 lines
15 KiB
C
658 lines
15 KiB
C
/*
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* Copyright (c) 2006-2022, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2013-07-20 Bernard first version
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* 2014-04-03 Grissiom many enhancements
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* 2018-11-22 Jesven add rt_hw_ipi_send()
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* add rt_hw_ipi_handler_install()
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* 2022-08-24 GuEe-GUI add pic support
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* 2022-11-07 GuEe-GUI add v2m support
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*/
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#include <rthw.h>
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#include <rtthread.h>
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#include <rtdevice.h>
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#define DBG_TAG "pic.gicv2"
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#define DBG_LVL DBG_INFO
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#include <rtdbg.h>
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#include <cpuport.h>
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#include <ioremap.h>
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#include "pic-gicv2.h"
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#include "pic-gic-common.h"
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#define GIC_CPU_IMAX 8
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#define raw_to_gicv2(raw) rt_container_of(raw, struct gicv2, parent)
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static rt_bool_t needs_rmw_access = RT_FALSE;
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static int _gicv2_nr = 0, _init_cpu_id = 0;
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static struct gicv2 _gicv2_list[RT_PIC_ARM_GIC_MAX_NR] = {};
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static rt_bool_t _gicv2_eoi_mode_ns = RT_FALSE;
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static rt_uint8_t _gicv2_cpumask_map[GIC_CPU_IMAX] =
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{
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[0 ... GIC_CPU_IMAX - 1] = 0xff,
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};
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static rt_uint8_t gicv2_cpumask_map(struct gicv2 *gic)
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{
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rt_uint32_t mask, i;
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for (i = mask = 0; i < 32; i += 4)
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{
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mask = HWREG32(gic->dist_base + GIC_DIST_TARGET + i);
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mask |= mask >> 16;
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mask |= mask >> 8;
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if (mask)
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{
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break;
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}
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}
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return mask;
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}
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static void gicv2_dist_init(struct gicv2 *gic)
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{
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void *base = gic->dist_base;
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rt_uint32_t i;
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rt_uint32_t cpumask = gicv2_cpumask_map(gic);
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_init_cpu_id = rt_hw_cpu_id();
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gic->max_irq = HWREG32(base + GIC_DIST_TYPE) & 0x1f;
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gic->max_irq = (gic->max_irq + 1) * 32;
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/*
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* The GIC only supports up to 1020 interrupt sources.
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* Limit this to either the architected maximum, or the
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* platform maximum.
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*/
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if (gic->max_irq > 1020)
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{
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gic->max_irq = 1020;
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}
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LOG_D("Max irq = %d", gic->max_irq);
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HWREG32(base + GIC_DIST_CTRL) = GICD_DISABLE;
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/* Set all global (unused) interrupts to this CPU only. */
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cpumask |= cpumask << 8;
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cpumask |= cpumask << 16;
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for (i = 32; i < gic->max_irq; i += 4)
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{
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HWREG32(base + GIC_DIST_TARGET + i * 4 / 4) = cpumask;
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}
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gic_common_dist_config(base, gic->max_irq, RT_NULL, RT_NULL);
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HWREG32(base + GIC_DIST_CTRL) = GICD_ENABLE;
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}
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static void gicv2_cpu_init(struct gicv2 *gic)
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{
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rt_uint32_t cpumask;
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void *base = gic->cpu_base;
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rt_uint32_t config = GICC_ENABLE;
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int cpu_id = rt_hw_cpu_id();
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cpumask = gicv2_cpumask_map(gic);
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_gicv2_cpumask_map[cpu_id] = cpumask;
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/*
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* Clear our mask from the other map entries in case they're
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* still undefined.
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*/
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for (int i = 0; i < RT_ARRAY_SIZE(_gicv2_cpumask_map); ++i)
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{
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if (i != cpu_id)
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{
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_gicv2_cpumask_map[i] &= ~cpumask;
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}
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}
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gic_common_cpu_config(gic->dist_base, 32, RT_NULL, RT_NULL);
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HWREG32(base + GIC_CPU_PRIMASK) = GICC_INT_PRI_THRESHOLD;
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HWREG32(base + GIC_CPU_BINPOINT) = 0x7;
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#ifdef ARCH_SUPPORT_HYP
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_gicv2_eoi_mode_ns = RT_TRUE;
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#endif
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if (_gicv2_eoi_mode_ns)
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{
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config |= GIC_CPU_CTRL_EOI_MODE_NS;
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}
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HWREG32(base + GIC_CPU_CTRL) = config;
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}
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static rt_err_t gicv2_irq_init(struct rt_pic *pic)
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{
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gicv2_cpu_init(rt_container_of(pic, struct gicv2, parent));
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return RT_EOK;
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}
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static void gicv2_irq_ack(struct rt_pic_irq *pirq)
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{
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int hwirq = pirq->hwirq;
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struct gicv2 *gic = raw_to_gicv2(pirq->pic);
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if (!_gicv2_eoi_mode_ns)
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{
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HWREG32(gic->dist_base + GIC_DIST_PENDING_CLEAR + hwirq / 32 * 4) = 1U << (hwirq % 32);
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}
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HWREG32(gic->cpu_base + GIC_CPU_EOI) = hwirq;
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}
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static void gicv2_irq_mask(struct rt_pic_irq *pirq)
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{
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int hwirq = pirq->hwirq;
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struct gicv2 *gic = raw_to_gicv2(pirq->pic);
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HWREG32(gic->dist_base + GIC_DIST_ENABLE_CLEAR + hwirq / 32 * 4) = 1U << (hwirq % 32);
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}
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static void gicv2_irq_unmask(struct rt_pic_irq *pirq)
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{
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int hwirq = pirq->hwirq;
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struct gicv2 *gic = raw_to_gicv2(pirq->pic);
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HWREG32(gic->dist_base + GIC_DIST_ENABLE_SET + hwirq / 32 * 4) = 1U << (hwirq % 32);
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}
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static void gicv2_irq_eoi(struct rt_pic_irq *pirq)
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{
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struct gicv2 *gic = raw_to_gicv2(pirq->pic);
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if (_gicv2_eoi_mode_ns)
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{
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HWREG32(gic->cpu_base + GIC_CPU_DIR) = pirq->hwirq;
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}
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}
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static rt_err_t gicv2_irq_set_priority(struct rt_pic_irq *pirq, rt_uint32_t priority)
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{
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rt_uint32_t mask;
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int hwirq = pirq->hwirq;
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struct gicv2 *gic = raw_to_gicv2(pirq->pic);
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mask = HWREG32(gic->dist_base + GIC_DIST_PRI + hwirq / 4 * 4);
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mask &= ~(0xffU << ((hwirq % 4) * 8));
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mask |= ((priority & 0xffU) << ((hwirq % 4) * 8));
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HWREG32(gic->dist_base + GIC_DIST_PRI + hwirq / 4 * 4) = mask;
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return RT_EOK;
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}
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static rt_err_t gicv2_irq_set_affinity(struct rt_pic_irq *pirq, rt_bitmap_t *affinity)
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{
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int hwirq = pirq->hwirq;
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struct gicv2 *gic = raw_to_gicv2(pirq->pic);
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rt_uint32_t target_list = ((rt_uint8_t *)affinity)[gic - &_gicv2_list[0]];
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rt_uint8_t valb = _gicv2_cpumask_map[__rt_ffs(target_list) - 1];
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void *io_addr = gic->dist_base + GIC_DIST_TARGET + hwirq;
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if (valb == 0xfe)
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{
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return -RT_EIO;
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}
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if (needs_rmw_access)
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{
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/* RMW write byte */
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rt_uint32_t val;
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rt_ubase_t level;
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rt_ubase_t offset = (rt_ubase_t)io_addr & 3UL, shift = offset * 8;
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static struct rt_spinlock rmw_lock = {};
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level = rt_spin_lock_irqsave(&rmw_lock);
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io_addr -= offset;
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val = HWREG32(io_addr);
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val &= ~RT_GENMASK(shift + 7, shift);
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val |= valb << shift;
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HWREG32(io_addr) = val;
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rt_spin_unlock_irqrestore(&rmw_lock, level);
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}
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else
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{
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HWREG8(io_addr) = valb;
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}
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return RT_EOK;
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}
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static rt_err_t gicv2_irq_set_triger_mode(struct rt_pic_irq *pirq, rt_uint32_t mode)
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{
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rt_err_t err = RT_EOK;
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int hwirq = pirq->hwirq;
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struct gicv2 *gic = raw_to_gicv2(pirq->pic);
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if (hwirq >= GIC_SGI_NR)
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{
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err = gic_common_configure_irq(gic->dist_base + GIC_DIST_CONFIG, pirq->hwirq, mode, RT_NULL, RT_NULL);
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}
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else
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{
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err = -RT_ENOSYS;
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}
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return err;
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}
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static void gicv2_irq_send_ipi(struct rt_pic_irq *pirq, rt_bitmap_t *cpumask)
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{
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struct gicv2 *gic;
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int sgi = pirq->hwirq;
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rt_uint8_t *target_list = (rt_uint8_t *)cpumask;
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for (int i = 0; i < _gicv2_nr; ++i)
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{
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if (*target_list)
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{
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gic = &_gicv2_list[i];
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HWREG32(gic->dist_base + GIC_DIST_SOFTINT) = ((*target_list & 0xffU) << 16) | (sgi & 0xf);
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rt_hw_dsb();
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}
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++target_list;
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}
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}
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static rt_err_t gicv2_irq_set_state(struct rt_pic *pic, int hwirq, int type, rt_bool_t state)
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{
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rt_err_t err = RT_EOK;
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rt_uint32_t offset = 0;
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struct gicv2 *gic = raw_to_gicv2(pic);
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switch (type)
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{
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case RT_IRQ_STATE_PENDING:
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offset = state ? GIC_DIST_PENDING_SET : GIC_DIST_PENDING_CLEAR;
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break;
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case RT_IRQ_STATE_ACTIVE:
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offset = state ? GIC_DIST_ACTIVE_SET : GIC_DIST_ACTIVE_CLEAR;
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break;
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case RT_IRQ_STATE_MASKED:
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offset = state ? GIC_DIST_ENABLE_CLEAR : GIC_DIST_ENABLE_SET;
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break;
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default:
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err = -RT_EINVAL;
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break;
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}
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if (!err)
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{
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rt_uint32_t mask = 1 << (hwirq % 32);
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HWREG32(gic->dist_base + offset + (hwirq / 32) * 4) = mask;
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}
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return err;
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}
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static rt_err_t gicv2_irq_get_state(struct rt_pic *pic, int hwirq, int type, rt_bool_t *out_state)
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{
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rt_err_t err = RT_EOK;
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rt_uint32_t offset = 0;
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struct gicv2 *gic = raw_to_gicv2(pic);
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switch (type)
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{
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case RT_IRQ_STATE_PENDING:
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offset = GIC_DIST_PENDING_SET;
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break;
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case RT_IRQ_STATE_ACTIVE:
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offset = GIC_DIST_ACTIVE_SET;
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break;
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case RT_IRQ_STATE_MASKED:
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offset = GIC_DIST_ENABLE_SET;
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break;
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default:
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err = -RT_EINVAL;
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break;
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}
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if (!err)
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{
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rt_uint32_t mask = 1 << (hwirq % 32);
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*out_state = !!(HWREG32(gic->dist_base + offset + (hwirq / 32) * 4) & mask);
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}
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return err;
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}
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static int gicv2_irq_map(struct rt_pic *pic, int hwirq, rt_uint32_t mode)
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{
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int irq, irq_index = hwirq - GIC_SGI_NR;
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struct rt_pic_irq *pirq = rt_pic_find_irq(pic, irq_index);
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if (pirq && hwirq >= GIC_SGI_NR)
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{
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pirq->mode = mode;
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pirq->priority = GICD_INT_DEF_PRI;
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if (hwirq < 32)
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{
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gic_fill_ppi_affinity(pirq->affinity);
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}
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else
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{
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RT_IRQ_AFFINITY_SET(pirq->affinity, _init_cpu_id);
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}
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irq = rt_pic_config_irq(pic, irq_index, hwirq);
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if (irq >= 0 && mode != RT_IRQ_MODE_LEVEL_HIGH)
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{
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gicv2_irq_set_triger_mode(pirq, mode);
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}
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}
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else
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{
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irq = -1;
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}
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return irq;
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}
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static rt_err_t gicv2_irq_parse(struct rt_pic *pic, struct rt_ofw_cell_args *args, struct rt_pic_irq *out_pirq)
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{
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rt_err_t err = RT_EOK;
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if (args->args_count == 3)
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{
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out_pirq->mode = args->args[2] & RT_IRQ_MODE_MASK;
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switch (args->args[0])
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{
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case 0:
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/* SPI */
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out_pirq->hwirq = args->args[1] + 32;
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break;
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case 1:
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/* PPI */
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out_pirq->hwirq = args->args[1] + 16;
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break;
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default:
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err = -RT_ENOSYS;
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break;
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}
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}
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else
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{
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err = -RT_EINVAL;
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}
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return err;
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}
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const static struct rt_pic_ops gicv2_ops =
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{
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.name = "GICv2",
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.irq_init = gicv2_irq_init,
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.irq_ack = gicv2_irq_ack,
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.irq_mask = gicv2_irq_mask,
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.irq_unmask = gicv2_irq_unmask,
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.irq_eoi = gicv2_irq_eoi,
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.irq_set_priority = gicv2_irq_set_priority,
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.irq_set_affinity = gicv2_irq_set_affinity,
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.irq_set_triger_mode = gicv2_irq_set_triger_mode,
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.irq_send_ipi = gicv2_irq_send_ipi,
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.irq_set_state = gicv2_irq_set_state,
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.irq_get_state = gicv2_irq_get_state,
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.irq_map = gicv2_irq_map,
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.irq_parse = gicv2_irq_parse,
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};
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static rt_bool_t gicv2_handler(void *data)
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{
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rt_bool_t res = RT_FALSE;
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int hwirq;
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struct gicv2 *gic = data;
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hwirq = HWREG32(gic->cpu_base + GIC_CPU_INTACK) & 0x3ffUL;
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if (!(hwirq >= 1020 && hwirq <= 1023))
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{
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struct rt_pic_irq *pirq;
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if (hwirq < GIC_SGI_NR)
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{
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rt_hw_rmb();
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pirq = rt_pic_find_ipi(&gic->parent, hwirq);
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}
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else
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{
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pirq = rt_pic_find_irq(&gic->parent, hwirq - GIC_SGI_NR);
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}
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gicv2_irq_ack(pirq);
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rt_pic_handle_isr(pirq);
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gicv2_irq_eoi(pirq);
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res = RT_TRUE;
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}
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return res;
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}
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static rt_err_t gicv2_enable_rmw_access(void *data)
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{
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if (rt_ofw_machine_is_compatible("renesas,emev2"))
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{
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needs_rmw_access = RT_TRUE;
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return RT_EOK;
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}
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return -RT_EINVAL;
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}
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static const struct gic_quirk _gicv2_quirks[] =
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{
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{
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.desc = "GICv2: Broken byte access",
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.compatible = "arm,pl390",
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.init = gicv2_enable_rmw_access,
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},
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{ /* sentinel */ }
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};
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static rt_err_t gicv2_iomap_init(struct gicv2 *gic, rt_uint64_t *regs)
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{
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rt_err_t err = RT_EOK;
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int idx;
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const char *name[] =
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{
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"Distributor",
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"CPU interfaces",
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"Virtual interface control",
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"Virtual CPU interface",
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};
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do {
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/* GICD->GICC->GICH->GICV */
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gic->dist_size = regs[1];
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gic->dist_base = rt_ioremap((void *)regs[0], gic->dist_size);
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if (!gic->dist_base)
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{
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idx = 0;
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err = -RT_ERROR;
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break;
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}
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gic->cpu_size = regs[3];
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gic->cpu_base = rt_ioremap((void *)regs[2], gic->cpu_size);
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if (!gic->cpu_base)
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{
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idx = 1;
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err = -RT_ERROR;
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break;
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}
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/* ArchRev[4:7] */
|
|
gic->version = HWREG32(gic->dist_base + GIC_DIST_ICPIDR2) >> 4;
|
|
|
|
#ifdef ARCH_SUPPORT_HYP
|
|
if (gic->version == 1)
|
|
{
|
|
break;
|
|
}
|
|
|
|
gic->hyp_size = regs[5];
|
|
gic->hyp_base = rt_ioremap((void *)regs[4], gic->hyp_size);
|
|
if (!gic->hyp_base)
|
|
{
|
|
idx = 2;
|
|
err = -RT_ERROR;
|
|
break;
|
|
}
|
|
|
|
gic->vcpu_size = regs[7];
|
|
gic->vcpu_base = rt_ioremap((void *)regs[6], gic->vcpu_size);
|
|
if (!gic->vcpu_base)
|
|
{
|
|
idx = 3;
|
|
err = -RT_ERROR;
|
|
break;
|
|
}
|
|
#endif /* ARCH_SUPPORT_HYP */
|
|
} while (0);
|
|
|
|
if (err)
|
|
{
|
|
RT_UNUSED(idx);
|
|
RT_UNUSED(name);
|
|
|
|
LOG_E("gic[%d] %s IO[%p, %p] map fail", _gicv2_nr, name[idx], regs[idx * 2], regs[idx * 2 + 1]);
|
|
}
|
|
|
|
return err;
|
|
}
|
|
|
|
static void gicv2_init(struct gicv2 *gic)
|
|
{
|
|
gicv2_dist_init(gic);
|
|
|
|
gic->parent.priv_data = gic;
|
|
gic->parent.ops = &gicv2_ops;
|
|
|
|
rt_pic_linear_irq(&gic->parent, gic->max_irq + 1 - GIC_SGI_NR);
|
|
gic_common_sgi_config(gic->dist_base, &gic->parent, _gicv2_nr * GIC_SGI_NR);
|
|
|
|
rt_pic_add_traps(gicv2_handler, gic);
|
|
|
|
rt_pic_user_extends(&gic->parent);
|
|
}
|
|
|
|
static void gicv2_init_fail(struct gicv2 *gic)
|
|
{
|
|
if (gic->dist_base)
|
|
{
|
|
rt_iounmap(gic->dist_base);
|
|
}
|
|
if (gic->cpu_base)
|
|
{
|
|
rt_iounmap(gic->cpu_base);
|
|
}
|
|
if (gic->hyp_base)
|
|
{
|
|
rt_iounmap(gic->hyp_base);
|
|
}
|
|
if (gic->vcpu_base)
|
|
{
|
|
rt_iounmap(gic->vcpu_base);
|
|
}
|
|
rt_memset(gic, 0, sizeof(*gic));
|
|
}
|
|
|
|
static rt_err_t gicv2_ofw_init(struct rt_ofw_node *np, const struct rt_ofw_node_id *id)
|
|
{
|
|
rt_err_t err = RT_EOK;
|
|
struct gicv2 *gic = RT_NULL;
|
|
|
|
do {
|
|
rt_uint64_t regs[8];
|
|
|
|
if (_gicv2_nr >= RT_PIC_ARM_GIC_MAX_NR)
|
|
{
|
|
LOG_W("GICv2/v1 table is full");
|
|
err = -RT_EFULL;
|
|
break;
|
|
}
|
|
|
|
gic = &_gicv2_list[_gicv2_nr];
|
|
|
|
rt_ofw_get_address_array(np, RT_ARRAY_SIZE(regs), regs);
|
|
|
|
if ((err = gicv2_iomap_init(gic, regs)))
|
|
{
|
|
break;
|
|
}
|
|
|
|
if (gic->version != 1 && gic->version != 2)
|
|
{
|
|
LOG_E("Version = %d is not support", gic->version);
|
|
err = -RT_EINVAL;
|
|
break;
|
|
}
|
|
|
|
gic_common_init_quirk_ofw(np, _gicv2_quirks, gic);
|
|
gicv2_init(gic);
|
|
|
|
rt_ofw_data(np) = &gic->parent;
|
|
|
|
if (gic->version == 2)
|
|
{
|
|
#ifdef RT_PIC_ARM_GIC_V2M
|
|
gicv2m_ofw_probe(np, id);
|
|
#endif
|
|
}
|
|
|
|
++_gicv2_nr;
|
|
} while (0);
|
|
|
|
if (err && gic)
|
|
{
|
|
gicv2_init_fail(gic);
|
|
}
|
|
|
|
return err;
|
|
}
|
|
|
|
static const struct rt_ofw_node_id gicv2_ofw_ids[] =
|
|
{
|
|
{ .compatible = "arm,gic-400" },
|
|
{ .compatible = "arm,arm11mp-gic" },
|
|
{ .compatible = "arm,arm1176jzf-devchip-gic" },
|
|
{ .compatible = "arm,cortex-a15-gic" },
|
|
{ .compatible = "arm,cortex-a9-gic" },
|
|
{ .compatible = "arm,cortex-a7-gic" },
|
|
{ .compatible = "qcom,msm-8660-qgic" },
|
|
{ .compatible = "qcom,msm-qgic2" },
|
|
{ .compatible = "arm,pl390" },
|
|
{ /* sentinel */ }
|
|
};
|
|
RT_PIC_OFW_DECLARE(gicv2, gicv2_ofw_ids, gicv2_ofw_init);
|