535 lines
16 KiB
C
535 lines
16 KiB
C
/** @file sys_vim.c
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* @brief VIM Driver Inmplmentation File
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* @date
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* @version 03.05.02
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*
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*/
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/* (c) Texas Instruments 2009-2013, All rights reserved. */
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#include "sys_vim.h"
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#include "system.h"
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/* Vim Ram Definition */
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/** @struct vimRam
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* @brief Vim Ram Definition
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*
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* This type is used to access the Vim Ram.
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*/
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/** @typedef vimRAM_t
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* @brief Vim Ram Type Definition
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*
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* This type is used to access the Vim Ram.
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*/
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typedef volatile struct vimRam
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{
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t_isrFuncPTR ISR[VIM_CHANNELS + 1U];
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} vimRAM_t;
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#define vimRAM ((vimRAM_t *)0xFFF82000U)
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/** @fn void vimInit(void)
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* @brief Initializes VIM module
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*
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* This function initializes VIM RAM and registers
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*/
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void vimInit(void)
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{
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/* Set Fall-Back Address Parity Error Register */
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/*VIM_FBPARERR = (uint32)&vimParityErrorHandler;*/
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/* set IRQ/FIQ priorities */
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vimREG->FIRQPR0 = SYS_FIQ
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| (SYS_FIQ << 1U)
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| (SYS_IRQ << 2U)
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| (SYS_IRQ << 3U)
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| (SYS_IRQ << 4U)
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| (SYS_IRQ << 5U)
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| (SYS_IRQ << 6U)
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| (SYS_IRQ << 7U)
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| (SYS_IRQ << 8U)
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| (SYS_IRQ << 9U)
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| (SYS_IRQ << 10U)
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| (SYS_IRQ << 11U)
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| (SYS_IRQ << 12U)
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| (SYS_IRQ << 13U)
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| (SYS_IRQ << 14U)
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| (SYS_IRQ << 15U)
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| (SYS_IRQ << 16U)
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| (SYS_IRQ << 17U)
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| (SYS_IRQ << 18U)
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| (SYS_IRQ << 19U)
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| (SYS_IRQ << 20U)
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| (SYS_IRQ << 21U)
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| (SYS_IRQ << 22U)
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| (SYS_IRQ << 23U)
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| (SYS_IRQ << 24U)
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| (SYS_IRQ << 25U)
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| (SYS_IRQ << 26U)
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| (SYS_IRQ << 27U)
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| (SYS_IRQ << 28U)
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| (SYS_IRQ << 29U)
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| (SYS_IRQ << 30U)
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| (SYS_IRQ << 31U);
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vimREG->FIRQPR1 = SYS_IRQ
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| (SYS_IRQ << 1U)
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| (SYS_IRQ << 2U)
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| (SYS_IRQ << 3U)
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| (SYS_IRQ << 4U)
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| (SYS_IRQ << 5U)
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| (SYS_IRQ << 6U)
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| (SYS_IRQ << 7U)
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| (SYS_IRQ << 8U)
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| (SYS_IRQ << 9U)
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| (SYS_IRQ << 10U)
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| (SYS_IRQ << 11U)
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| (SYS_IRQ << 12U)
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| (SYS_IRQ << 13U)
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| (SYS_IRQ << 14U)
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| (SYS_IRQ << 15U)
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| (SYS_IRQ << 16U)
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| (SYS_IRQ << 17U)
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| (SYS_IRQ << 18U)
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| (SYS_IRQ << 19U)
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| (SYS_IRQ << 20U)
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| (SYS_IRQ << 21U)
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| (SYS_IRQ << 22U)
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| (SYS_IRQ << 23U)
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| (SYS_IRQ << 24U)
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| (SYS_IRQ << 25U)
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| (SYS_IRQ << 26U)
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| (SYS_IRQ << 27U)
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| (SYS_IRQ << 28U)
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| (SYS_IRQ << 29U)
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| (SYS_IRQ << 30U)
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| (SYS_IRQ << 31U);
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vimREG->FIRQPR2 = SYS_IRQ
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| (SYS_IRQ << 1U)
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| (SYS_IRQ << 2U)
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| (SYS_IRQ << 3U)
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| (SYS_IRQ << 4U)
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| (SYS_IRQ << 5U)
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| (SYS_IRQ << 6U)
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| (SYS_IRQ << 7U)
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| (SYS_IRQ << 8U)
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| (SYS_IRQ << 9U)
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| (SYS_IRQ << 10U)
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| (SYS_IRQ << 11U)
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| (SYS_IRQ << 12U)
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| (SYS_IRQ << 13U)
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| (SYS_IRQ << 14U)
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| (SYS_IRQ << 15U)
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| (SYS_IRQ << 16U)
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| (SYS_IRQ << 17U)
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| (SYS_IRQ << 18U)
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| (SYS_IRQ << 19U)
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| (SYS_IRQ << 20U)
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| (SYS_IRQ << 21U)
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| (SYS_IRQ << 22U)
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| (SYS_IRQ << 23U)
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| (SYS_IRQ << 24U)
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| (SYS_IRQ << 25U)
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| (SYS_IRQ << 26U)
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| (SYS_IRQ << 27U)
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| (SYS_IRQ << 28U)
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| (SYS_IRQ << 29U)
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| (SYS_IRQ << 30U)
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| (SYS_IRQ << 31U);
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vimREG->FIRQPR3 = SYS_IRQ
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| (SYS_IRQ << 1U)
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| (SYS_IRQ << 2U)
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| (SYS_IRQ << 3U)
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| (SYS_IRQ << 4U)
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| (SYS_IRQ << 5U)
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| (SYS_IRQ << 6U)
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| (SYS_IRQ << 7U)
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| (SYS_IRQ << 8U)
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| (SYS_IRQ << 9U)
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| (SYS_IRQ << 10U)
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| (SYS_IRQ << 11U)
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| (SYS_IRQ << 12U)
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| (SYS_IRQ << 13U)
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| (SYS_IRQ << 14U)
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| (SYS_IRQ << 15U)
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| (SYS_IRQ << 16U)
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| (SYS_IRQ << 17U)
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| (SYS_IRQ << 18U)
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| (SYS_IRQ << 19U)
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| (SYS_IRQ << 20U)
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| (SYS_IRQ << 21U)
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| (SYS_IRQ << 22U)
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| (SYS_IRQ << 23U)
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| (SYS_IRQ << 24U)
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| (SYS_IRQ << 25U)
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| (SYS_IRQ << 26U)
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| (SYS_IRQ << 27U)
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| (SYS_IRQ << 28U)
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| (SYS_IRQ << 29U)
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| (SYS_IRQ << 30U)
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| (SYS_IRQ << 31U);
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/* enable interrupts */
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vimREG->REQMASKSET0 = 1U
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| (1U << 1U)
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| (0U << 2U)
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| (0U << 3U)
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| (0U << 4U)
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| (1U << 5U)
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| (0U << 6U)
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| (0U << 7U)
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| (0U << 8U)
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| (0U << 9U)
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| (0U << 10U)
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| (0U << 11U)
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| (0U << 12U)
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| (1U << 13U)
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| (0U << 14U)
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| (0U << 15U)
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| (0U << 16U)
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| (0U << 17U)
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| (0U << 18U)
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| (0U << 19U)
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| (0U << 20U)
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| (0U << 21U)
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| (0U << 22U)
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| (0U << 23U)
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| (0U << 24U)
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| (0U << 25U)
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| (0U << 26U)
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| (0U << 27U)
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| (0U << 28U)
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| (0U << 29U)
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| (0U << 30U)
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| (0U << 31U);
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vimREG->REQMASKSET1 = 0U
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| (0U << 1U)
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| (0U << 2U)
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| (0U << 3U)
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| (0U << 4U)
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| (0U << 5U)
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| (0U << 6U)
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| (0U << 7U)
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| (0U << 8U)
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| (0U << 9U)
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| (0U << 10U)
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| (0U << 11U)
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| (0U << 12U)
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| (0U << 13U)
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| (0U << 14U)
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| (0U << 15U)
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| (0U << 16U)
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| (0U << 17U)
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| (0U << 18U)
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| (0U << 19U)
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| (0U << 20U)
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| (0U << 21U)
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| (0U << 22U)
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| (0U << 23U)
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| (0U << 24U)
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| (0U << 25U)
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| (0U << 26U)
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| (0U << 27U)
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| (0U << 28U)
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| (0U << 29U)
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| (0U << 30U)
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| (0U << 31U);
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vimREG->REQMASKSET2 = 0U
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| (0U << 1U)
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| (0U << 2U)
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| (0U << 3U)
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| (0U << 4U)
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| (0U << 5U)
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| (0U << 6U)
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| (0U << 7U)
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| (0U << 8U)
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| (0U << 9U)
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| (0U << 10U)
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| (0U << 11U)
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| (0U << 12U)
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| (0U << 13U)
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| (0U << 14U)
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| (0U << 15U)
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| (0U << 16U)
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| (0U << 17U)
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| (0U << 18U)
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| (0U << 19U)
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| (0U << 20U)
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| (0U << 21U)
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| (0U << 22U)
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| (0U << 23U)
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| (0U << 24U)
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| (0U << 25U)
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| (0U << 26U)
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| (0U << 27U)
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| (0U << 28U)
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| (0U << 29U)
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| (0U << 30U)
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| (0U << 31U);
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vimREG->REQMASKSET3 = 0U
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| (0U << 1U)
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| (0U << 2U)
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| (0U << 3U)
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| (0U << 4U)
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| (0U << 5U)
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| (0U << 6U)
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| (0U << 7U)
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| (0U << 8U)
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| (0U << 9U)
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| (0U << 10U)
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| (0U << 11U)
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| (0U << 12U)
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| (0U << 13U)
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| (0U << 14U)
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| (0U << 15U)
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| (0U << 16U)
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| (0U << 17U)
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| (0U << 18U)
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| (0U << 19U)
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| (0U << 20U)
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| (0U << 21U)
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| (0U << 22U)
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| (0U << 23U)
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| (0U << 24U)
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| (0U << 25U)
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| (0U << 26U)
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| (0U << 27U)
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| (0U << 28U)
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| (0U << 29U)
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| (0U << 30U)
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| (0U << 31U);
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}
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/** @fn void vimChannelMap(uint32 request, uint32 channel, t_isrFuncPTR handler)
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* @brief Map selected interrupt request to the selected channel
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*
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* @param[in] request: Interrupt request number 2..95
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* @param[in] channel: VIM Channel number 2..95
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* @param[in] handler: Address of the interrupt handler
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*
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* This function will map selected interrupt request to the selected channel.
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*
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*/
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void vimChannelMap(uint32 request, uint32 channel, t_isrFuncPTR handler)
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{
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uint32 i,j;
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i = channel >> 2U; /* Find the register to configure */
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j = channel -(i<<2U); /* Find the offset of the type */
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j = 3U-j; /* reverse the byte order */
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j = j<<3U; /* find the bit location */
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/*Mapping the required interrupt request to the required channel*/
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vimREG->CHANCTRL[i] &= ~(0xFFU << j);
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vimREG->CHANCTRL[i] |= (request << j);
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/*Updating VIMRAM*/
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vimRAM->ISR[channel+1] = handler;
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}
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/** @fn void vimEnableInterrupt(uint32 channel, boolean inttype)
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* @brief Enable interrupt for the the selected channel
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*
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* @param[in] channel: VIM Channel number 2..95
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* @param[in] handler: Interrupt type
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* - SYS_IRQ: Selected channel will be enabled as IRQ
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* - SYS_FIQ: Selected channel will be enabled as FIQ
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*
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* This function will enable interrupt for the selected channel.
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*
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*/
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void vimEnableInterrupt(uint32 channel, boolean inttype)
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{
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if (channel >= 64)
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{
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if(inttype == SYS_IRQ)
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{
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vimREG->FIRQPR2 &= ~(1 << (channel-64));
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}
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else
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{
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vimREG->FIRQPR2 |= 1 << (channel-64);
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}
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vimREG->REQMASKSET2 = 1 << (channel-64);
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}
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else if (channel >= 32)
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{
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if(inttype == SYS_IRQ)
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{
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vimREG->FIRQPR1 &= ~(1 << (channel-32));
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}
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else
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{
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vimREG->FIRQPR1 |= 1 << (channel-32);
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}
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vimREG->REQMASKSET1 = 1 << (channel-32);
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}
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else if (channel >= 2)
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{
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if(inttype == SYS_IRQ)
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{
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vimREG->FIRQPR0 &= ~(1 << channel);
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}
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else
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{
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vimREG->FIRQPR0 |= 1 << channel;
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}
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vimREG->REQMASKSET0 = 1 << channel;
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}
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else
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{
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}
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}
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/** @fn void vimDisableInterrupt(uint32 channel)
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* @brief Disable interrupt for the the selected channel
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*
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* @param[in] channel: VIM Channel number 2..95
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*
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* This function will disable interrupt for the selected channel.
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*
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*/
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void vimDisableInterrupt(uint32 channel)
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{
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if (channel >= 64)
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{
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vimREG->REQMASKCLR2 = 1 << (channel-64);
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}
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else if (channel >=32)
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{
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vimREG->REQMASKCLR1 = 1 << (channel-32);
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}
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else if (channel >= 2)
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{
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vimREG->REQMASKCLR0 = 1 << channel;
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}
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else
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{
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}
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}
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/** @fn void vimGetConfigValue(vim_config_reg_t *config_reg, config_value_type_t type)
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* @brief Get the initial or current values of the configuration registers
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*
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* @param[in] *config_reg: pointer to the struct to which the initial or current value of the configuration registers need to be stored
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* @param[in] type: whether initial or current value of the configuration registers need to be stored
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* - InitialValue: initial value of the configuration registers will be stored in the struct pointed by config_reg
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* - CurrentValue: initial value of the configuration registers will be stored in the struct pointed by config_reg
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*
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* This function will copy the initial or current value (depending on the parameter 'type') of the configuration registers to the struct pointed by config_reg
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*
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*/
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void vimGetConfigValue(vim_config_reg_t *config_reg, config_value_type_t type)
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{
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uint32 temp[24U] = VIM_CHANCTRL_CONFIGVALUE;
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uint32 i;
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if (type == InitialValue)
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{
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config_reg->CONFIG_FIRQPR0 = VIM_FIRQPR0_CONFIGVALUE;
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config_reg->CONFIG_FIRQPR1 = VIM_FIRQPR1_CONFIGVALUE;
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config_reg->CONFIG_FIRQPR2 = VIM_FIRQPR2_CONFIGVALUE;
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config_reg->CONFIG_FIRQPR3 = VIM_FIRQPR3_CONFIGVALUE;
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config_reg->CONFIG_REQMASKSET0 = VIM_REQMASKSET0_CONFIGVALUE;
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config_reg->CONFIG_REQMASKSET1 = VIM_REQMASKSET1_CONFIGVALUE;
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config_reg->CONFIG_REQMASKSET2 = VIM_REQMASKSET2_CONFIGVALUE;
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config_reg->CONFIG_REQMASKSET3 = VIM_REQMASKSET3_CONFIGVALUE;
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config_reg->CONFIG_WAKEMASKSET0 = VIM_WAKEMASKSET0_CONFIGVALUE;
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config_reg->CONFIG_WAKEMASKSET1 = VIM_WAKEMASKSET1_CONFIGVALUE;
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config_reg->CONFIG_WAKEMASKSET2 = VIM_WAKEMASKSET2_CONFIGVALUE;
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config_reg->CONFIG_WAKEMASKSET3 = VIM_WAKEMASKSET3_CONFIGVALUE;
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config_reg->CONFIG_CAPEVT = VIM_CAPEVT_CONFIGVALUE;
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for (i=0U; i<24U;i++)
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{
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config_reg->CONFIG_CHANCTRL[i] = temp[i];
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}
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}
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else
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{
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config_reg->CONFIG_FIRQPR0 = vimREG->FIRQPR0;
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config_reg->CONFIG_FIRQPR1 = vimREG->FIRQPR1;
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config_reg->CONFIG_FIRQPR2 = vimREG->FIRQPR2;
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config_reg->CONFIG_FIRQPR3 = vimREG->FIRQPR3;
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config_reg->CONFIG_REQMASKSET0 = vimREG->REQMASKSET0;
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config_reg->CONFIG_REQMASKSET1 = vimREG->REQMASKSET1;
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config_reg->CONFIG_REQMASKSET2 = vimREG->REQMASKSET2;
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config_reg->CONFIG_REQMASKSET3 = vimREG->REQMASKSET3;
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config_reg->CONFIG_WAKEMASKSET0 = vimREG->WAKEMASKSET0;
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config_reg->CONFIG_WAKEMASKSET1 = vimREG->WAKEMASKSET1;
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config_reg->CONFIG_WAKEMASKSET2 = vimREG->WAKEMASKSET2;
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config_reg->CONFIG_WAKEMASKSET3 = vimREG->WAKEMASKSET3;
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config_reg->CONFIG_CAPEVT = vimREG->CAPEVT;
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for (i=0U; i<24U; i++)
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{
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config_reg->CONFIG_CHANCTRL[i] = vimREG->CHANCTRL[i];
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}
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}
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}
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#if 0
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#pragma CODE_STATE(vimParityErrorHandler, 32)
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#pragma INTERRUPT(vimParityErrorHandler, IRQ)
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void vimParityErrorHandler(void)
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{
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/* Identify the corrupted address */
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uint32 error_addr = VIM_ADDERR;
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/* Identify the channel number */
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uint32 error_channel = ((error_addr & 0x1FF) >> 2) - 1;
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/* Correct the corrupted location */
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vimRAM->ISR[error_channel + 1] = s_vim_init[error_channel + 1];
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/* Clear Parity Error Flag */
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VIM_PARFLG = 1;
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/* Disable and enable the highest priority pending channel */
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sint32 channel;
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channel = vimREG->FIQINDEX - 1;
|
|
if (vimREG->FIQINDEX != 0)
|
|
{
|
|
channel = vimREG->FIQINDEX - 1;
|
|
}
|
|
else
|
|
{
|
|
channel = vimREG->IRQINDEX - 1;
|
|
}
|
|
if (channel >= 0)
|
|
{
|
|
if (channel < 32)
|
|
{
|
|
vimREG->REQMASKCLR0 = 1 << channel;
|
|
vimREG->REQMASKSET0 = 1 << channel;
|
|
}
|
|
else if (channel < 64)
|
|
{
|
|
vimREG->REQMASKCLR1 = 1 << (channel-32);
|
|
vimREG->REQMASKSET1 = 1 << (channel-32);
|
|
}
|
|
else
|
|
{
|
|
vimREG->REQMASKCLR2 = 1 << (channel-64);
|
|
vimREG->REQMASKSET2 = 1 << (channel-64);
|
|
}
|
|
}
|
|
}
|
|
#endif
|