1153 lines
40 KiB
C
1153 lines
40 KiB
C
/*
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* Copyright (C) 2010 - 2019 Xilinx, Inc.
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* Copyright (C) 2021 WangHuachen.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
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* SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
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* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
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* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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* OF SUCH DAMAGE.
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*
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* This file is part of the lwIP TCP/IP stack.
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*
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*/
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/*****************************************************************************
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* This file xemacpsif_physpeed.c implements functionalities to:
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* - Detect the available PHYs connected to a MAC
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* - Negotiate speed
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* - Configure speed
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* - Configure the SLCR registers for the negotiated speed
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*
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* In a typical use case, users of the APIs implemented in this file need to
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* do the following.
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* - Call the API detect_phy. It probes for the available PHYs connected to a MAC.
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* The MACs can be Emac0 (XPAR_XEMACPS_0_BASEADDR, 0xE000B000) or Emac1
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* (XPAR_XEMACPS_0_BASEADDR, 0xE000C000). It populates an array to notify
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* about the detected PHYs. The array phymapemac0 is used for Emac0 and
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* phymapemac1 is for Emac1.
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* - The users need to parse the corresponding arrays, phymapemac0 or phymapemac1
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* to know the available PHYs for a MAC. The users then need to call
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* phy_setup_emacps to setup the PHYs for proper speed setting. The API
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* phy_setup_emacps should be called with the PHY address for which the speed
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* needs to be negotiated or configured. In a specific use case, if 2 PHYs are
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* connected to Emac0 with addresses of 7 and 11, then users get these address
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* details from phymapemac0 (after calling detect_phy) and then call
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* phy_setup_emacps twice, with ab address of 7 and 11.
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* - Points to note: The MAC can operate at only one speed. If a MAC is connected
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* to multiple PHYs, then all PHYs must negotiate and configured for the same
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* speed.
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* - This file implements static functions to set proper SLCR clocks. As stated
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* above, all PHYs connected to a PHY must operate at same speed and the SLCR
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* clock will be setup accordingly.
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*
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* This file implements the following PHY types.
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* - The standard RGMII.
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* - It provides support for GMII to RGMII converter Xilinx IP. This Xilinx IP
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* sits on the MDIO bus with a predefined PHY address. This IP exposes register
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* that needs to be programmed with the negotiated speed.
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* For example, in a typical design, the Emac0 or Emac1 exposes GMII interface.
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* The user can then use the Xilinx IP that converts GMII to RGMII.
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* The external PHY (most typically Marvell 88E1116R) negotiates for speed
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* with the remote PHY. The implementation in this file then programs the
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* Xilinx IP with this negotiated speed. The Xilinx IP has a predefined IP
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* address exposed through xparameters.h
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* - The SGMII and 1000 BaseX PHY interfaces.
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* If the PHY interface is SGMII or 1000 BaseX a separate "get_IEEE_phy_speed"
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* is used which is different from standard RGMII "get_IEEE_phy_speed".
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* The 1000 BaseX always operates at 1000 Mbps. The SGMII interface can
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* negotiate speed accordingly.
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* For SGMII or 1000 BaseX interfaces, the detect_phy should not be called.
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* The phy addresses for these interfaces are fixed at the design time.
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*
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* Point to note:
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* A MAC can not be connected to PHYs where there is a mix between
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* SGMII or 1000 Basex or GMII/MII/RGMII.
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* In a typical multiple PHY designs, it is expected that the PHYs connected
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* will be RGMII or GMII.
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*
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* The users can choose not to negotiate speed from lwip settings GUI.
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* If they opt to choose a particular PHY speed, then the PHY will hard code
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* the speed to operate only at the corresponding speed. It will not advertise
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* any other speeds. It is users responsibility to ensure that the remote PHY
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* supports the speed programmed through the lwip gui.
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*
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* The following combination of MDIO/PHY are supported:
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* - Multiple PHYs connected to the MDIO bus of a MAC. If Emac0 MDIO is connected
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* to single/multiple PHYs, it is supported. Similarly Emac1 MDIO connected to
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* single/multiple PHYs is supported.
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* - A design where both the interfaces are present and are connected to their own
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* MDIO bus is supported.
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*
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* The following MDIO/PHY setup is not supported:
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* - A design has both the MACs present. MDIO bus is available only for one MAC
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* (Emac0 or Emac1). This MDIO bus has multiple PHYs available for both the
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* MACs. The negotiated speed for PHYs sitting on the MDIO bus of one MAC will
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* not be see for the other MAC and hence the speed/SLCR settings of the other
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* MAC cannot be programmed. Hence this kind of design will not work for
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* this implementation.
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*
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********************************************************************************/
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#include "netif/xemacpsif.h"
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#include "lwipopts.h"
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#include "xparameters_ps.h"
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#include "xparameters.h"
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#include "xemac_ieee_reg.h"
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#if defined (__aarch64__)
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#include "bspconfig.h"
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#include "xil_smc.h"
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#endif
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#define CONFIG_LINKSPEED_AUTODETECT 1
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#define PHY_DETECT_REG 1
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#define PHY_IDENTIFIER_1_REG 2
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#define PHY_IDENTIFIER_2_REG 3
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#define PHY_DETECT_MASK 0x1808
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#define PHY_MARVELL_IDENTIFIER 0x0141
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#define PHY_TI_IDENTIFIER 0x2000
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#define PHY_REALTEK_IDENTIFIER 0x001c
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#define PHY_XILINX_PCS_PMA_ID1 0x0174
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#define PHY_XILINX_PCS_PMA_ID2 0x0C00
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#define XEMACPS_GMII2RGMII_SPEED1000_FD 0x140
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#define XEMACPS_GMII2RGMII_SPEED100_FD 0x2100
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#define XEMACPS_GMII2RGMII_SPEED10_FD 0x100
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#define XEMACPS_GMII2RGMII_REG_NUM 0x10
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#define PHY_REGCR 0x0D
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#define PHY_ADDAR 0x0E
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#define PHY_RGMIIDCTL 0x86
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#define PHY_RGMIICTL 0x32
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#define PHY_STS 0x11
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#define PHY_TI_CR 0x10
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#define PHY_TI_CFG4 0x31
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#define MICREL_PHY_IDENTIFIER 0x22
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#define MICREL_PHY_KSZ9031_MODEL 0x220
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#define PHY_REGCR_ADDR 0x001F
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#define PHY_REGCR_DATA 0x401F
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#define PHY_TI_CRVAL 0x5048
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#define PHY_TI_CFG4RESVDBIT7 0x80
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/* Frequency setting */
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#define SLCR_LOCK_ADDR (XPS_SYS_CTRL_BASEADDR + 0x4)
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#define SLCR_UNLOCK_ADDR (XPS_SYS_CTRL_BASEADDR + 0x8)
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#define SLCR_GEM0_CLK_CTRL_ADDR (XPS_SYS_CTRL_BASEADDR + 0x140)
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#define SLCR_GEM1_CLK_CTRL_ADDR (XPS_SYS_CTRL_BASEADDR + 0x144)
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#define SLCR_GEM_SRCSEL_EMIO 0x40
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#define SLCR_LOCK_KEY_VALUE 0x767B
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#define SLCR_UNLOCK_KEY_VALUE 0xDF0D
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#define SLCR_ADDR_GEM_RST_CTRL (XPS_SYS_CTRL_BASEADDR + 0x214)
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#define EMACPS_SLCR_DIV_MASK 0xFC0FC0FF
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#if XPAR_GIGE_PCS_PMA_1000BASEX_CORE_PRESENT == 1 || \
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XPAR_GIGE_PCS_PMA_SGMII_CORE_PRESENT == 1
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#define PCM_PMA_CORE_PRESENT
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#else
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#undef PCM_PMA_CORE_PRESENT
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#endif
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#ifdef PCM_PMA_CORE_PRESENT
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#define IEEE_CTRL_RESET 0x9140
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#define IEEE_CTRL_ISOLATE_DISABLE 0xFBFF
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#endif
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u32_t phymapemac0[32];
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u32_t phymapemac1[32];
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#if defined (PCM_PMA_CORE_PRESENT) || defined (CONFIG_LINKSPEED_AUTODETECT)
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static u32_t get_IEEE_phy_speed(XEmacPs *xemacpsp, u32_t phy_addr);
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#endif
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static void SetUpSLCRDivisors(u32_t mac_baseaddr, s32_t speed);
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#if defined (CONFIG_LINKSPEED1000) || defined (CONFIG_LINKSPEED100) \
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|| defined (CONFIG_LINKSPEED10)
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static u32_t configure_IEEE_phy_speed(XEmacPs *xemacpsp, u32_t phy_addr, u32_t speed);
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#endif
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#ifdef PCM_PMA_CORE_PRESENT
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u32_t phy_setup_emacps (XEmacPs *xemacpsp, u32_t phy_addr)
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{
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u32_t link_speed;
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u16_t regval;
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u16_t phy_id;
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if(phy_addr == 0) {
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for (phy_addr = 31; phy_addr > 0; phy_addr--) {
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XEmacPs_PhyRead(xemacpsp, phy_addr, PHY_IDENTIFIER_1_REG,
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&phy_id);
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if (phy_id == PHY_XILINX_PCS_PMA_ID1) {
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XEmacPs_PhyRead(xemacpsp, phy_addr, PHY_IDENTIFIER_2_REG,
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&phy_id);
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if (phy_id == PHY_XILINX_PCS_PMA_ID2) {
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/* Found a valid PHY address */
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LWIP_DEBUGF(NETIF_DEBUG, ("XEmacPs detect_phy: PHY detected at address %d.\r\n",
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phy_addr));
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break;
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}
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}
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}
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}
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link_speed = get_IEEE_phy_speed(xemacpsp, phy_addr);
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if (link_speed == 1000)
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SetUpSLCRDivisors(xemacpsp->Config.BaseAddress,1000);
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else if (link_speed == 100)
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SetUpSLCRDivisors(xemacpsp->Config.BaseAddress,100);
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else
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SetUpSLCRDivisors(xemacpsp->Config.BaseAddress,10);
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xil_printf("link speed for phy address %d: %d\r\n", phy_addr, link_speed);
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return link_speed;
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}
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static u32_t get_IEEE_phy_speed(XEmacPs *xemacpsp, u32_t phy_addr)
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{
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u16_t temp;
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u16_t control;
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u16_t status;
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u16_t partner_capabilities;
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xil_printf("Start PHY autonegotiation \r\n");
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XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_CONTROL_REG_OFFSET, &control);
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control |= IEEE_CTRL_AUTONEGOTIATE_ENABLE;
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control |= IEEE_STAT_AUTONEGOTIATE_RESTART;
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control &= IEEE_CTRL_ISOLATE_DISABLE;
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XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_CONTROL_REG_OFFSET, control);
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xil_printf("Waiting for PHY to complete autonegotiation.\r\n");
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XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_STATUS_REG_OFFSET, &status);
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while ( !(status & IEEE_STAT_AUTONEGOTIATE_COMPLETE) ) {
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sleep(1);
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XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_STATUS_REG_OFFSET,
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&status);
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}
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xil_printf("autonegotiation complete \r\n");
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#if XPAR_GIGE_PCS_PMA_1000BASEX_CORE_PRESENT == 1
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XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_PAGE_ADDRESS_REGISTER, 1);
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XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_PARTNER_ABILITIES_1_REG_OFFSET, &temp);
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if ((temp & 0x0020) == 0x0020) {
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XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_PAGE_ADDRESS_REGISTER, 0);
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return 1000;
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}
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else {
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XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_PAGE_ADDRESS_REGISTER, 0);
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xil_printf("Link error, temp = %x\r\n", temp);
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return 0;
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}
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#elif XPAR_GIGE_PCS_PMA_SGMII_CORE_PRESENT == 1
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xil_printf("Waiting for Link to be up; Polling for SGMII core Reg \r\n");
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XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_PARTNER_ABILITIES_1_REG_OFFSET, &temp);
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while(!(temp & 0x8000)) {
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XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_PARTNER_ABILITIES_1_REG_OFFSET, &temp);
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}
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if((temp & 0x0C00) == 0x0800) {
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return 1000;
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}
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else if((temp & 0x0C00) == 0x0400) {
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return 100;
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}
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else if((temp & 0x0C00) == 0x0000) {
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return 10;
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} else {
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xil_printf("get_IEEE_phy_speed(): Invalid speed bit value, Defaulting to Speed = 10 Mbps\r\n");
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XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_CONTROL_REG_OFFSET, &temp);
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XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_CONTROL_REG_OFFSET, 0x0100);
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return 10;
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}
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#endif
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}
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#else /*PCM_PMA_CORE_PRESENT not defined, GMII/RGMII case*/
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void detect_phy(XEmacPs *xemacpsp)
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{
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u16_t phy_reg;
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u32_t phy_addr;
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u32_t emacnum;
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if (xemacpsp->Config.BaseAddress == XPAR_XEMACPS_0_BASEADDR)
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emacnum = 0;
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else
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emacnum = 1;
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for (phy_addr = 31; phy_addr > 0; phy_addr--) {
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XEmacPs_PhyRead(xemacpsp, phy_addr, PHY_DETECT_REG,
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&phy_reg);
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if ((phy_reg != 0xFFFF) &&
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((phy_reg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
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/* Found a valid PHY address */
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LWIP_DEBUGF(NETIF_DEBUG, ("XEmacPs detect_phy: PHY detected at address %d.\r\n",
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phy_addr));
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if (emacnum == 0)
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phymapemac0[phy_addr] = TRUE;
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else
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phymapemac1[phy_addr] = TRUE;
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XEmacPs_PhyRead(xemacpsp, phy_addr, PHY_IDENTIFIER_1_REG,
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&phy_reg);
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if ((phy_reg != PHY_MARVELL_IDENTIFIER) &&
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(phy_reg != PHY_TI_IDENTIFIER) &&
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(phy_reg != PHY_REALTEK_IDENTIFIER)) {
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xil_printf("WARNING: Not a Marvell or TI or Realtek Ethernet PHY. Please verify the initialization sequence\r\n");
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}
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}
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}
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}
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u32_t phy_setup_emacps (XEmacPs *xemacpsp, u32_t phy_addr)
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{
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u32_t link_speed;
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u32_t conv_present = 0;
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u32_t convspeeddupsetting = 0;
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u32_t convphyaddr = 0;
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#ifdef XPAR_GMII2RGMIICON_0N_ETH0_ADDR
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convphyaddr = XPAR_GMII2RGMIICON_0N_ETH0_ADDR;
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conv_present = 1;
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#endif
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#ifdef XPAR_GMII2RGMIICON_0N_ETH1_ADDR
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convphyaddr = XPAR_GMII2RGMIICON_0N_ETH1_ADDR;
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conv_present = 1;
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#endif
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#ifdef CONFIG_LINKSPEED_AUTODETECT
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link_speed = get_IEEE_phy_speed(xemacpsp, phy_addr);
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if (link_speed == 1000) {
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SetUpSLCRDivisors(xemacpsp->Config.BaseAddress,1000);
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convspeeddupsetting = XEMACPS_GMII2RGMII_SPEED1000_FD;
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} else if (link_speed == 100) {
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SetUpSLCRDivisors(xemacpsp->Config.BaseAddress,100);
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convspeeddupsetting = XEMACPS_GMII2RGMII_SPEED100_FD;
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} else if (link_speed != XST_FAILURE){
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SetUpSLCRDivisors(xemacpsp->Config.BaseAddress,10);
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convspeeddupsetting = XEMACPS_GMII2RGMII_SPEED10_FD;
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} else {
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xil_printf("Phy setup error \r\n");
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return XST_FAILURE;
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}
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#elif defined(CONFIG_LINKSPEED1000)
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SetUpSLCRDivisors(xemacpsp->Config.BaseAddress,1000);
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link_speed = 1000;
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configure_IEEE_phy_speed(xemacpsp, phy_addr, link_speed);
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convspeeddupsetting = XEMACPS_GMII2RGMII_SPEED1000_FD;
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sleep(1);
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#elif defined(CONFIG_LINKSPEED100)
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SetUpSLCRDivisors(xemacpsp->Config.BaseAddress,100);
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link_speed = 100;
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configure_IEEE_phy_speed(xemacpsp, phy_addr, link_speed);
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convspeeddupsetting = XEMACPS_GMII2RGMII_SPEED100_FD;
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sleep(1);
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#elif defined(CONFIG_LINKSPEED10)
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SetUpSLCRDivisors(xemacpsp->Config.BaseAddress,10);
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link_speed = 10;
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configure_IEEE_phy_speed(xemacpsp, phy_addr, link_speed);
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convspeeddupsetting = XEMACPS_GMII2RGMII_SPEED10_FD;
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sleep(1);
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#endif
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if (conv_present) {
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XEmacPs_PhyWrite(xemacpsp, convphyaddr,
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XEMACPS_GMII2RGMII_REG_NUM, convspeeddupsetting);
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}
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xil_printf("link speed for phy address %d: %d\r\n", phy_addr, link_speed);
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return link_speed;
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}
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#if defined CONFIG_LINKSPEED_AUTODETECT
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static u32_t get_phy_speed_ksz9031(XEmacPs *xemacpsp, u32_t phy_addr)
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{
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static int phy_init_flag = 0;
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u16_t temp;
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u16_t control;
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u16_t status;
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u16_t status_speed;
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u32_t timeout_counter = 0;
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xil_printf("Start PHY autonegotiation \r\n");
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XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_PAGE_ADDRESS_REGISTER, 2);
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XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_CONTROL_REG_MAC, &control);
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control |= IEEE_RGMII_TXRX_CLOCK_DELAYED_MASK;
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XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_CONTROL_REG_MAC, control);
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XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_PAGE_ADDRESS_REGISTER, 0);
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|
|
XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_AUTONEGO_ADVERTISE_REG, &control);
|
|
control |= IEEE_ASYMMETRIC_PAUSE_MASK;
|
|
control |= IEEE_PAUSE_MASK;
|
|
control |= ADVERTISE_100;
|
|
control |= ADVERTISE_10;
|
|
XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_AUTONEGO_ADVERTISE_REG, control);
|
|
|
|
XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_1000_ADVERTISE_REG_OFFSET,
|
|
&control);
|
|
control |= ADVERTISE_1000;
|
|
XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_1000_ADVERTISE_REG_OFFSET,
|
|
control);
|
|
|
|
XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_PAGE_ADDRESS_REGISTER, 0);
|
|
XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_COPPER_SPECIFIC_CONTROL_REG, &control);
|
|
|
|
control |= (7 << 12); /* max number of gigabit attempts */
|
|
control |= (1 << 11); /* enable downshift */
|
|
XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_COPPER_SPECIFIC_CONTROL_REG,
|
|
control);
|
|
|
|
XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_CONTROL_REG_OFFSET, &control);
|
|
control |= IEEE_CTRL_AUTONEGOTIATE_ENABLE;
|
|
control |= IEEE_STAT_AUTONEGOTIATE_RESTART;
|
|
XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_CONTROL_REG_OFFSET, control);
|
|
|
|
XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_CONTROL_REG_OFFSET, &control);
|
|
control |= IEEE_CTRL_RESET_MASK;
|
|
XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_CONTROL_REG_OFFSET, control);
|
|
|
|
while (1) {
|
|
XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_CONTROL_REG_OFFSET, &control);
|
|
if (control & IEEE_CTRL_RESET_MASK)
|
|
continue;
|
|
else
|
|
break;
|
|
}
|
|
|
|
XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_STATUS_REG_OFFSET, &status);
|
|
|
|
xil_printf("Waiting for PHY to complete autonegotiation.\r\n");
|
|
|
|
while (!(status & IEEE_STAT_AUTONEGOTIATE_COMPLETE)) {
|
|
sleep(1);
|
|
XEmacPs_PhyRead(xemacpsp, phy_addr,
|
|
IEEE_COPPER_SPECIFIC_STATUS_REG_2, &temp);
|
|
timeout_counter++;
|
|
if ((phy_init_flag == 0) && (timeout_counter > 1))
|
|
{
|
|
phy_init_flag = 1;
|
|
return XST_FAILURE;
|
|
}
|
|
if (timeout_counter == 30) {
|
|
xil_printf("Auto negotiation error \r\n");
|
|
return XST_FAILURE;
|
|
}
|
|
XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_STATUS_REG_OFFSET, &status);
|
|
}
|
|
xil_printf("autonegotiation complete \r\n");
|
|
|
|
XEmacPs_PhyRead(xemacpsp, phy_addr, 0x1f, &status_speed);
|
|
|
|
if ((status_speed & 0x40) == 0x40) /* 1000Mbps */
|
|
return 1000;
|
|
else if ((status_speed & 0x20) == 0x20) /* 100Mbps */
|
|
return 100;
|
|
else if ((status_speed & 0x10) == 0x10) /* 10Mbps */
|
|
return 10;
|
|
else
|
|
return 0;
|
|
return XST_SUCCESS;
|
|
}
|
|
|
|
static u32_t get_TI_phy_speed(XEmacPs *xemacpsp, u32_t phy_addr)
|
|
{
|
|
u16_t control;
|
|
u16_t status;
|
|
u16_t status_speed;
|
|
u32_t timeout_counter = 0;
|
|
u32_t phyregtemp;
|
|
int i;
|
|
u32_t RetStatus;
|
|
static int phy_init_flag = 0;
|
|
|
|
xil_printf("Start PHY autonegotiation \r\n");
|
|
|
|
XEmacPs_PhyRead(xemacpsp, phy_addr, 0x1F, (u16_t *)&phyregtemp);
|
|
phyregtemp |= 0x4000;
|
|
XEmacPs_PhyWrite(xemacpsp, phy_addr, 0x1F, phyregtemp);
|
|
RetStatus = XEmacPs_PhyRead(xemacpsp, phy_addr, 0x1F, (u16_t *)&phyregtemp);
|
|
if (RetStatus != XST_SUCCESS) {
|
|
xil_printf("Error during sw reset \n\r");
|
|
return XST_FAILURE;
|
|
}
|
|
|
|
XEmacPs_PhyRead(xemacpsp, phy_addr, 0, (u16_t *)&phyregtemp);
|
|
phyregtemp |= 0x8000;
|
|
XEmacPs_PhyWrite(xemacpsp, phy_addr, 0, phyregtemp);
|
|
|
|
/*
|
|
* Delay
|
|
*/
|
|
for(i=0;i<1000000000;i++);
|
|
|
|
RetStatus = XEmacPs_PhyRead(xemacpsp, phy_addr, 0, (u16_t *)&phyregtemp);
|
|
if (RetStatus != XST_SUCCESS) {
|
|
xil_printf("Error during reset \n\r");
|
|
return XST_FAILURE;
|
|
}
|
|
|
|
/* FIFO depth */
|
|
XEmacPs_PhyWrite(xemacpsp, phy_addr, PHY_TI_CR, PHY_TI_CRVAL);
|
|
RetStatus = XEmacPs_PhyRead(xemacpsp, phy_addr, PHY_TI_CR, (u16_t *)&phyregtemp);
|
|
if (RetStatus != XST_SUCCESS) {
|
|
xil_printf("Error writing to 0x10 \n\r");
|
|
return XST_FAILURE;
|
|
}
|
|
|
|
/* TX/RX tuning */
|
|
/* Write to PHY_RGMIIDCTL */
|
|
XEmacPs_PhyWrite(xemacpsp, phy_addr, PHY_REGCR, PHY_REGCR_ADDR);
|
|
XEmacPs_PhyWrite(xemacpsp, phy_addr, PHY_ADDAR, PHY_RGMIIDCTL);
|
|
XEmacPs_PhyWrite(xemacpsp, phy_addr, PHY_REGCR, PHY_REGCR_DATA);
|
|
RetStatus = XEmacPs_PhyWrite(xemacpsp, phy_addr, PHY_ADDAR, 0xA8);
|
|
if (RetStatus != XST_SUCCESS) {
|
|
xil_printf("Error in tuning");
|
|
return XST_FAILURE;
|
|
}
|
|
|
|
/* Read PHY_RGMIIDCTL */
|
|
XEmacPs_PhyWrite(xemacpsp, phy_addr, PHY_REGCR, PHY_REGCR_ADDR);
|
|
XEmacPs_PhyWrite(xemacpsp, phy_addr, PHY_ADDAR, PHY_RGMIIDCTL);
|
|
XEmacPs_PhyWrite(xemacpsp, phy_addr, PHY_REGCR, PHY_REGCR_DATA);
|
|
RetStatus = XEmacPs_PhyRead(xemacpsp, phy_addr, PHY_ADDAR, (u16_t *)&phyregtemp);
|
|
if (RetStatus != XST_SUCCESS) {
|
|
xil_printf("Error in tuning");
|
|
return XST_FAILURE;
|
|
}
|
|
|
|
/* Write PHY_RGMIICTL */
|
|
XEmacPs_PhyWrite(xemacpsp, phy_addr, PHY_REGCR, PHY_REGCR_ADDR);
|
|
XEmacPs_PhyWrite(xemacpsp, phy_addr, PHY_ADDAR, PHY_RGMIICTL);
|
|
XEmacPs_PhyWrite(xemacpsp, phy_addr, PHY_REGCR, PHY_REGCR_DATA);
|
|
RetStatus = XEmacPs_PhyWrite(xemacpsp, phy_addr, PHY_ADDAR, 0xD3);
|
|
if (RetStatus != XST_SUCCESS) {
|
|
xil_printf("Error in tuning");
|
|
return XST_FAILURE;
|
|
}
|
|
|
|
/* Read PHY_RGMIICTL */
|
|
XEmacPs_PhyWrite(xemacpsp, phy_addr, PHY_REGCR, PHY_REGCR_ADDR);
|
|
XEmacPs_PhyWrite(xemacpsp, phy_addr, PHY_ADDAR, PHY_RGMIICTL);
|
|
XEmacPs_PhyWrite(xemacpsp, phy_addr, PHY_REGCR, PHY_REGCR_DATA);
|
|
RetStatus = XEmacPs_PhyRead(xemacpsp, phy_addr, PHY_ADDAR, (u16_t *)&phyregtemp);
|
|
if (RetStatus != XST_SUCCESS) {
|
|
xil_printf("Error in tuning");
|
|
return XST_FAILURE;
|
|
}
|
|
|
|
/* SW workaround for unstable link when RX_CTRL is not STRAP MODE 3 or 4 */
|
|
XEmacPs_PhyWrite(xemacpsp, phy_addr, PHY_REGCR, PHY_REGCR_ADDR);
|
|
XEmacPs_PhyWrite(xemacpsp, phy_addr, PHY_ADDAR, PHY_TI_CFG4);
|
|
XEmacPs_PhyWrite(xemacpsp, phy_addr, PHY_REGCR, PHY_REGCR_DATA);
|
|
RetStatus = XEmacPs_PhyRead(xemacpsp, phy_addr, PHY_ADDAR, (u16_t *)&phyregtemp);
|
|
phyregtemp &= ~(PHY_TI_CFG4RESVDBIT7);
|
|
XEmacPs_PhyWrite(xemacpsp, phy_addr, PHY_REGCR, PHY_REGCR_ADDR);
|
|
XEmacPs_PhyWrite(xemacpsp, phy_addr, PHY_ADDAR, PHY_TI_CFG4);
|
|
XEmacPs_PhyWrite(xemacpsp, phy_addr, PHY_REGCR, PHY_REGCR_DATA);
|
|
RetStatus = XEmacPs_PhyWrite(xemacpsp, phy_addr, PHY_ADDAR, phyregtemp);
|
|
|
|
XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_AUTONEGO_ADVERTISE_REG, &control);
|
|
control |= IEEE_ASYMMETRIC_PAUSE_MASK;
|
|
control |= IEEE_PAUSE_MASK;
|
|
control |= ADVERTISE_100;
|
|
control |= ADVERTISE_10;
|
|
XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_AUTONEGO_ADVERTISE_REG, control);
|
|
|
|
XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_1000_ADVERTISE_REG_OFFSET,
|
|
&control);
|
|
control |= ADVERTISE_1000;
|
|
XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_1000_ADVERTISE_REG_OFFSET,
|
|
control);
|
|
|
|
XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_CONTROL_REG_OFFSET, &control);
|
|
control |= IEEE_CTRL_AUTONEGOTIATE_ENABLE;
|
|
control |= IEEE_STAT_AUTONEGOTIATE_RESTART;
|
|
XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_CONTROL_REG_OFFSET, control);
|
|
|
|
XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_CONTROL_REG_OFFSET, &control);
|
|
XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_STATUS_REG_OFFSET, &status);
|
|
|
|
xil_printf("Waiting for PHY to complete autonegotiation.\r\n");
|
|
|
|
while ( !(status & IEEE_STAT_AUTONEGOTIATE_COMPLETE) ) {
|
|
sleep(1);
|
|
timeout_counter++;
|
|
if ((phy_init_flag == 0) && (timeout_counter > 1))
|
|
{
|
|
phy_init_flag = 1;
|
|
return XST_FAILURE;
|
|
}
|
|
if (timeout_counter == 30) {
|
|
xil_printf("Auto negotiation error \r\n");
|
|
return XST_FAILURE;
|
|
}
|
|
XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_STATUS_REG_OFFSET, &status);
|
|
}
|
|
xil_printf("autonegotiation complete \r\n");
|
|
|
|
XEmacPs_PhyRead(xemacpsp, phy_addr, PHY_STS, &status_speed);
|
|
if ((status_speed & 0xC000) == 0x8000) {
|
|
return 1000;
|
|
} else if ((status_speed & 0xC000) == 0x4000) {
|
|
return 100;
|
|
} else {
|
|
return 10;
|
|
}
|
|
|
|
return XST_SUCCESS;
|
|
}
|
|
|
|
static u32_t get_Marvell_phy_speed(XEmacPs *xemacpsp, u32_t phy_addr)
|
|
{
|
|
u16_t temp;
|
|
u16_t control;
|
|
u16_t status;
|
|
u16_t status_speed;
|
|
u32_t timeout_counter = 0;
|
|
u32_t temp_speed;
|
|
static int phy_init_flag = 0;
|
|
|
|
xil_printf("Start PHY autonegotiation \r\n");
|
|
|
|
XEmacPs_PhyWrite(xemacpsp,phy_addr, IEEE_PAGE_ADDRESS_REGISTER, 2);
|
|
XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_CONTROL_REG_MAC, &control);
|
|
control |= IEEE_RGMII_TXRX_CLOCK_DELAYED_MASK;
|
|
XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_CONTROL_REG_MAC, control);
|
|
|
|
XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_PAGE_ADDRESS_REGISTER, 0);
|
|
|
|
XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_AUTONEGO_ADVERTISE_REG, &control);
|
|
control |= IEEE_ASYMMETRIC_PAUSE_MASK;
|
|
control |= IEEE_PAUSE_MASK;
|
|
control |= ADVERTISE_100;
|
|
control |= ADVERTISE_10;
|
|
XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_AUTONEGO_ADVERTISE_REG, control);
|
|
|
|
XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_1000_ADVERTISE_REG_OFFSET,
|
|
&control);
|
|
control |= ADVERTISE_1000;
|
|
XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_1000_ADVERTISE_REG_OFFSET,
|
|
control);
|
|
|
|
XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_PAGE_ADDRESS_REGISTER, 0);
|
|
XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_COPPER_SPECIFIC_CONTROL_REG,
|
|
&control);
|
|
control |= (7 << 12); /* max number of gigabit attempts */
|
|
control |= (1 << 11); /* enable downshift */
|
|
XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_COPPER_SPECIFIC_CONTROL_REG,
|
|
control);
|
|
XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_CONTROL_REG_OFFSET, &control);
|
|
control |= IEEE_CTRL_AUTONEGOTIATE_ENABLE;
|
|
control |= IEEE_STAT_AUTONEGOTIATE_RESTART;
|
|
XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_CONTROL_REG_OFFSET, control);
|
|
|
|
XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_CONTROL_REG_OFFSET, &control);
|
|
control |= IEEE_CTRL_RESET_MASK;
|
|
XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_CONTROL_REG_OFFSET, control);
|
|
|
|
while (1) {
|
|
XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_CONTROL_REG_OFFSET, &control);
|
|
if (control & IEEE_CTRL_RESET_MASK)
|
|
continue;
|
|
else
|
|
break;
|
|
}
|
|
|
|
XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_STATUS_REG_OFFSET, &status);
|
|
|
|
xil_printf("Waiting for PHY to complete autonegotiation.\r\n");
|
|
|
|
while ( !(status & IEEE_STAT_AUTONEGOTIATE_COMPLETE) ) {
|
|
sleep(1);
|
|
XEmacPs_PhyRead(xemacpsp, phy_addr,
|
|
IEEE_COPPER_SPECIFIC_STATUS_REG_2, &temp);
|
|
timeout_counter++;
|
|
if ((phy_init_flag == 0) && (timeout_counter > 1))
|
|
{
|
|
phy_init_flag = 1;
|
|
return XST_FAILURE;
|
|
}
|
|
if (timeout_counter == 30) {
|
|
xil_printf("Auto negotiation error \r\n");
|
|
return XST_FAILURE;
|
|
}
|
|
XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_STATUS_REG_OFFSET, &status);
|
|
}
|
|
xil_printf("autonegotiation complete \r\n");
|
|
|
|
XEmacPs_PhyRead(xemacpsp, phy_addr,IEEE_SPECIFIC_STATUS_REG,
|
|
&status_speed);
|
|
if (status_speed & 0x400) {
|
|
temp_speed = status_speed & IEEE_SPEED_MASK;
|
|
|
|
if (temp_speed == IEEE_SPEED_1000)
|
|
return 1000;
|
|
else if(temp_speed == IEEE_SPEED_100)
|
|
return 100;
|
|
else
|
|
return 10;
|
|
}
|
|
|
|
return XST_SUCCESS;
|
|
}
|
|
|
|
static u32_t get_Realtek_phy_speed(XEmacPs *xemacpsp, u32_t phy_addr)
|
|
{
|
|
u16_t control;
|
|
u16_t status;
|
|
u16_t status_speed;
|
|
u32_t timeout_counter = 0;
|
|
u32_t temp_speed;
|
|
static int phy_init_flag = 0;
|
|
|
|
xil_printf("Start PHY autonegotiation \r\n");
|
|
|
|
XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_AUTONEGO_ADVERTISE_REG, &control);
|
|
control |= IEEE_ASYMMETRIC_PAUSE_MASK;
|
|
control |= IEEE_PAUSE_MASK;
|
|
control |= ADVERTISE_100;
|
|
control |= ADVERTISE_10;
|
|
XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_AUTONEGO_ADVERTISE_REG, control);
|
|
|
|
XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_1000_ADVERTISE_REG_OFFSET,
|
|
&control);
|
|
control |= ADVERTISE_1000;
|
|
XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_1000_ADVERTISE_REG_OFFSET,
|
|
control);
|
|
|
|
XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_CONTROL_REG_OFFSET, &control);
|
|
control |= IEEE_CTRL_AUTONEGOTIATE_ENABLE;
|
|
control |= IEEE_STAT_AUTONEGOTIATE_RESTART;
|
|
XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_CONTROL_REG_OFFSET, control);
|
|
|
|
XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_CONTROL_REG_OFFSET, &control);
|
|
control |= IEEE_CTRL_RESET_MASK;
|
|
XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_CONTROL_REG_OFFSET, control);
|
|
|
|
while (1) {
|
|
XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_CONTROL_REG_OFFSET, &control);
|
|
if (control & IEEE_CTRL_RESET_MASK)
|
|
continue;
|
|
else
|
|
break;
|
|
}
|
|
|
|
XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_STATUS_REG_OFFSET, &status);
|
|
|
|
xil_printf("Waiting for PHY to complete autonegotiation.\r\n");
|
|
|
|
while ( !(status & IEEE_STAT_AUTONEGOTIATE_COMPLETE) ) {
|
|
sleep(1);
|
|
timeout_counter++;
|
|
if ((phy_init_flag == 0) && (timeout_counter > 1))
|
|
{
|
|
phy_init_flag = 1;
|
|
return XST_FAILURE;
|
|
}
|
|
if (timeout_counter == 30) {
|
|
xil_printf("Auto negotiation error \r\n");
|
|
return XST_FAILURE;
|
|
}
|
|
XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_STATUS_REG_OFFSET, &status);
|
|
}
|
|
xil_printf("autonegotiation complete \r\n");
|
|
|
|
XEmacPs_PhyRead(xemacpsp, phy_addr,IEEE_SPECIFIC_STATUS_REG,
|
|
&status_speed);
|
|
if (status_speed & 0x400) {
|
|
temp_speed = status_speed & IEEE_SPEED_MASK;
|
|
|
|
if (temp_speed == IEEE_SPEED_1000)
|
|
return 1000;
|
|
else if(temp_speed == IEEE_SPEED_100)
|
|
return 100;
|
|
else
|
|
return 10;
|
|
}
|
|
|
|
return XST_FAILURE;
|
|
}
|
|
|
|
static u32_t get_IEEE_phy_speed(XEmacPs *xemacpsp, u32_t phy_addr)
|
|
{
|
|
u16_t phy_identity;
|
|
u32_t RetStatus;
|
|
|
|
XEmacPs_PhyRead(xemacpsp, phy_addr, PHY_IDENTIFIER_1_REG,
|
|
&phy_identity);
|
|
if(phy_identity == MICREL_PHY_IDENTIFIER){
|
|
RetStatus = get_phy_speed_ksz9031(xemacpsp, phy_addr);
|
|
} else if (phy_identity == PHY_TI_IDENTIFIER) {
|
|
RetStatus = get_TI_phy_speed(xemacpsp, phy_addr);
|
|
} else if (phy_identity == PHY_REALTEK_IDENTIFIER) {
|
|
RetStatus = get_Realtek_phy_speed(xemacpsp, phy_addr);
|
|
} else {
|
|
RetStatus = get_Marvell_phy_speed(xemacpsp, phy_addr);
|
|
}
|
|
|
|
return RetStatus;
|
|
}
|
|
#endif
|
|
|
|
#if defined (CONFIG_LINKSPEED1000) || defined (CONFIG_LINKSPEED100) \
|
|
|| defined (CONFIG_LINKSPEED10)
|
|
static u32_t configure_IEEE_phy_speed(XEmacPs *xemacpsp, u32_t phy_addr, u32_t speed)
|
|
{
|
|
u16_t control;
|
|
u16_t autonereg;
|
|
|
|
XEmacPs_PhyWrite(xemacpsp,phy_addr, IEEE_PAGE_ADDRESS_REGISTER, 2);
|
|
XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_CONTROL_REG_MAC, &control);
|
|
control |= IEEE_RGMII_TXRX_CLOCK_DELAYED_MASK;
|
|
XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_CONTROL_REG_MAC, control);
|
|
|
|
XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_PAGE_ADDRESS_REGISTER, 0);
|
|
|
|
XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_AUTONEGO_ADVERTISE_REG, &autonereg);
|
|
autonereg |= IEEE_ASYMMETRIC_PAUSE_MASK;
|
|
autonereg |= IEEE_PAUSE_MASK;
|
|
XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_AUTONEGO_ADVERTISE_REG, autonereg);
|
|
|
|
XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_CONTROL_REG_OFFSET, &control);
|
|
control &= ~IEEE_CTRL_LINKSPEED_1000M;
|
|
control &= ~IEEE_CTRL_LINKSPEED_100M;
|
|
control &= ~IEEE_CTRL_LINKSPEED_10M;
|
|
|
|
if (speed == 1000) {
|
|
control |= IEEE_CTRL_LINKSPEED_1000M;
|
|
|
|
/* Don't advertise PHY speed of 100 Mbps */
|
|
XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_AUTONEGO_ADVERTISE_REG, &autonereg);
|
|
autonereg &= (~ADVERTISE_100);
|
|
XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_AUTONEGO_ADVERTISE_REG, autonereg);
|
|
|
|
/* Don't advertise PHY speed of 10 Mbps */
|
|
XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_AUTONEGO_ADVERTISE_REG, &autonereg);
|
|
autonereg &= (~ADVERTISE_10);
|
|
XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_AUTONEGO_ADVERTISE_REG, autonereg);
|
|
|
|
/* Advertise PHY speed of 1000 Mbps */
|
|
XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_1000_ADVERTISE_REG_OFFSET, &autonereg);
|
|
autonereg |= ADVERTISE_1000;
|
|
XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_1000_ADVERTISE_REG_OFFSET, autonereg);
|
|
}
|
|
|
|
else if (speed == 100) {
|
|
control |= IEEE_CTRL_LINKSPEED_100M;
|
|
|
|
/* Don't advertise PHY speed of 1000 Mbps */
|
|
XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_1000_ADVERTISE_REG_OFFSET, &autonereg);
|
|
autonereg &= (~ADVERTISE_1000);
|
|
XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_1000_ADVERTISE_REG_OFFSET, autonereg);
|
|
|
|
/* Don't advertise PHY speed of 10 Mbps */
|
|
XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_AUTONEGO_ADVERTISE_REG, &autonereg);
|
|
autonereg &= (~ADVERTISE_10);
|
|
XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_AUTONEGO_ADVERTISE_REG, autonereg);
|
|
|
|
/* Advertise PHY speed of 100 Mbps */
|
|
XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_AUTONEGO_ADVERTISE_REG, &autonereg);
|
|
autonereg |= ADVERTISE_100;
|
|
XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_AUTONEGO_ADVERTISE_REG, autonereg);
|
|
}
|
|
|
|
else if (speed == 10) {
|
|
control |= IEEE_CTRL_LINKSPEED_10M;
|
|
|
|
/* Don't advertise PHY speed of 1000 Mbps */
|
|
XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_1000_ADVERTISE_REG_OFFSET, &autonereg);
|
|
autonereg &= (~ADVERTISE_1000);
|
|
XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_1000_ADVERTISE_REG_OFFSET, autonereg);
|
|
|
|
/* Don't advertise PHY speed of 100 Mbps */
|
|
XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_AUTONEGO_ADVERTISE_REG, &autonereg);
|
|
autonereg &= (~ADVERTISE_100);
|
|
XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_AUTONEGO_ADVERTISE_REG, autonereg);
|
|
|
|
/* Advertise PHY speed of 10 Mbps */
|
|
XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_AUTONEGO_ADVERTISE_REG, &autonereg);
|
|
autonereg |= ADVERTISE_10;
|
|
XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_AUTONEGO_ADVERTISE_REG, autonereg);
|
|
}
|
|
|
|
XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_CONTROL_REG_OFFSET,
|
|
control | IEEE_CTRL_RESET_MASK);
|
|
{
|
|
volatile s32_t wait;
|
|
for (wait=0; wait < 100000; wait++);
|
|
}
|
|
return 0;
|
|
}
|
|
#endif
|
|
#endif /*PCM_PMA_CORE_PRESENT*/
|
|
|
|
static void SetUpSLCRDivisors(u32_t mac_baseaddr, s32_t speed)
|
|
{
|
|
volatile u32_t slcrBaseAddress;
|
|
u32_t SlcrDiv0 = 0;
|
|
u32_t SlcrDiv1 = 0;
|
|
u32_t SlcrTxClkCntrl;
|
|
u32_t gigeversion;
|
|
volatile u32_t CrlApbBaseAddr;
|
|
u32_t CrlApbDiv0 = 0;
|
|
u32_t CrlApbDiv1 = 0;
|
|
u32_t CrlApbGemCtrl;
|
|
#if EL1_NONSECURE
|
|
u32_t ClkId;
|
|
#endif
|
|
|
|
gigeversion = ((Xil_In32(mac_baseaddr + 0xFC)) >> 16) & 0xFFF;
|
|
if (gigeversion == 2) {
|
|
|
|
*(volatile u32_t *)(SLCR_UNLOCK_ADDR) = SLCR_UNLOCK_KEY_VALUE;
|
|
|
|
if (mac_baseaddr == ZYNQ_EMACPS_0_BASEADDR) {
|
|
slcrBaseAddress = SLCR_GEM0_CLK_CTRL_ADDR;
|
|
} else {
|
|
slcrBaseAddress = SLCR_GEM1_CLK_CTRL_ADDR;
|
|
}
|
|
|
|
if((*(volatile u32_t *)(UINTPTR)(slcrBaseAddress)) &
|
|
SLCR_GEM_SRCSEL_EMIO) {
|
|
return;
|
|
}
|
|
|
|
if (speed == 1000) {
|
|
if (mac_baseaddr == XPAR_XEMACPS_0_BASEADDR) {
|
|
#ifdef XPAR_PS7_ETHERNET_0_ENET_SLCR_1000MBPS_DIV0
|
|
SlcrDiv0 = XPAR_PS7_ETHERNET_0_ENET_SLCR_1000MBPS_DIV0;
|
|
SlcrDiv1 = XPAR_PS7_ETHERNET_0_ENET_SLCR_1000MBPS_DIV1;
|
|
#endif
|
|
} else {
|
|
#ifdef XPAR_PS7_ETHERNET_1_ENET_SLCR_1000MBPS_DIV0
|
|
SlcrDiv0 = XPAR_PS7_ETHERNET_1_ENET_SLCR_1000MBPS_DIV0;
|
|
SlcrDiv1 = XPAR_PS7_ETHERNET_1_ENET_SLCR_1000MBPS_DIV1;
|
|
#endif
|
|
}
|
|
} else if (speed == 100) {
|
|
if (mac_baseaddr == XPAR_XEMACPS_0_BASEADDR) {
|
|
#ifdef XPAR_PS7_ETHERNET_0_ENET_SLCR_100MBPS_DIV0
|
|
SlcrDiv0 = XPAR_PS7_ETHERNET_0_ENET_SLCR_100MBPS_DIV0;
|
|
SlcrDiv1 = XPAR_PS7_ETHERNET_0_ENET_SLCR_100MBPS_DIV1;
|
|
#endif
|
|
} else {
|
|
#ifdef XPAR_PS7_ETHERNET_1_ENET_SLCR_100MBPS_DIV0
|
|
SlcrDiv0 = XPAR_PS7_ETHERNET_1_ENET_SLCR_100MBPS_DIV0;
|
|
SlcrDiv1 = XPAR_PS7_ETHERNET_1_ENET_SLCR_100MBPS_DIV1;
|
|
#endif
|
|
}
|
|
} else {
|
|
if (mac_baseaddr == XPAR_XEMACPS_0_BASEADDR) {
|
|
#ifdef XPAR_PS7_ETHERNET_0_ENET_SLCR_10MBPS_DIV0
|
|
SlcrDiv0 = XPAR_PS7_ETHERNET_0_ENET_SLCR_10MBPS_DIV0;
|
|
SlcrDiv1 = XPAR_PS7_ETHERNET_0_ENET_SLCR_10MBPS_DIV1;
|
|
#endif
|
|
} else {
|
|
#ifdef XPAR_PS7_ETHERNET_1_ENET_SLCR_10MBPS_DIV0
|
|
SlcrDiv0 = XPAR_PS7_ETHERNET_1_ENET_SLCR_10MBPS_DIV0;
|
|
SlcrDiv1 = XPAR_PS7_ETHERNET_1_ENET_SLCR_10MBPS_DIV1;
|
|
#endif
|
|
}
|
|
}
|
|
|
|
if (SlcrDiv0 != 0 && SlcrDiv1 != 0) {
|
|
SlcrTxClkCntrl = *(volatile u32_t *)(UINTPTR)(slcrBaseAddress);
|
|
SlcrTxClkCntrl &= EMACPS_SLCR_DIV_MASK;
|
|
SlcrTxClkCntrl |= (SlcrDiv1 << 20);
|
|
SlcrTxClkCntrl |= (SlcrDiv0 << 8);
|
|
*(volatile u32_t *)(UINTPTR)(slcrBaseAddress) = SlcrTxClkCntrl;
|
|
*(volatile u32_t *)(SLCR_LOCK_ADDR) = SLCR_LOCK_KEY_VALUE;
|
|
} else {
|
|
xil_printf("Clock Divisors incorrect - Please check\r\n");
|
|
}
|
|
} else if (gigeversion == GEM_VERSION_ZYNQMP) {
|
|
/* Setup divisors in CRL_APB for Zynq Ultrascale+ MPSoC */
|
|
if (mac_baseaddr == ZYNQMP_EMACPS_0_BASEADDR) {
|
|
CrlApbBaseAddr = CRL_APB_GEM0_REF_CTRL;
|
|
} else if (mac_baseaddr == ZYNQMP_EMACPS_1_BASEADDR) {
|
|
CrlApbBaseAddr = CRL_APB_GEM1_REF_CTRL;
|
|
} else if (mac_baseaddr == ZYNQMP_EMACPS_2_BASEADDR) {
|
|
CrlApbBaseAddr = CRL_APB_GEM2_REF_CTRL;
|
|
} else if (mac_baseaddr == ZYNQMP_EMACPS_3_BASEADDR) {
|
|
CrlApbBaseAddr = CRL_APB_GEM3_REF_CTRL;
|
|
}
|
|
|
|
if (speed == 1000) {
|
|
if (mac_baseaddr == ZYNQMP_EMACPS_0_BASEADDR) {
|
|
#ifdef XPAR_PSU_ETHERNET_0_ENET_SLCR_1000MBPS_DIV0
|
|
CrlApbDiv0 = XPAR_PSU_ETHERNET_0_ENET_SLCR_1000MBPS_DIV0;
|
|
CrlApbDiv1 = XPAR_PSU_ETHERNET_0_ENET_SLCR_1000MBPS_DIV1;
|
|
#endif
|
|
} else if (mac_baseaddr == ZYNQMP_EMACPS_1_BASEADDR) {
|
|
#ifdef XPAR_PSU_ETHERNET_1_ENET_SLCR_1000MBPS_DIV0
|
|
CrlApbDiv0 = XPAR_PSU_ETHERNET_1_ENET_SLCR_1000MBPS_DIV0;
|
|
CrlApbDiv1 = XPAR_PSU_ETHERNET_1_ENET_SLCR_1000MBPS_DIV1;
|
|
#endif
|
|
} else if (mac_baseaddr == ZYNQMP_EMACPS_2_BASEADDR) {
|
|
#ifdef XPAR_PSU_ETHERNET_2_ENET_SLCR_1000MBPS_DIV0
|
|
CrlApbDiv0 = XPAR_PSU_ETHERNET_2_ENET_SLCR_1000MBPS_DIV0;
|
|
CrlApbDiv1 = XPAR_PSU_ETHERNET_2_ENET_SLCR_1000MBPS_DIV1;
|
|
#endif
|
|
} else if (mac_baseaddr == ZYNQMP_EMACPS_3_BASEADDR) {
|
|
#ifdef XPAR_PSU_ETHERNET_3_ENET_SLCR_1000MBPS_DIV0
|
|
CrlApbDiv0 = XPAR_PSU_ETHERNET_3_ENET_SLCR_1000MBPS_DIV0;
|
|
CrlApbDiv1 = XPAR_PSU_ETHERNET_3_ENET_SLCR_1000MBPS_DIV1;
|
|
#endif
|
|
}
|
|
} else if (speed == 100) {
|
|
if (mac_baseaddr == ZYNQMP_EMACPS_0_BASEADDR) {
|
|
#ifdef XPAR_PSU_ETHERNET_0_ENET_SLCR_100MBPS_DIV0
|
|
CrlApbDiv0 = XPAR_PSU_ETHERNET_0_ENET_SLCR_100MBPS_DIV0;
|
|
CrlApbDiv1 = XPAR_PSU_ETHERNET_0_ENET_SLCR_100MBPS_DIV1;
|
|
#endif
|
|
} else if (mac_baseaddr == ZYNQMP_EMACPS_1_BASEADDR) {
|
|
#ifdef XPAR_PSU_ETHERNET_1_ENET_SLCR_100MBPS_DIV0
|
|
CrlApbDiv0 = XPAR_PSU_ETHERNET_1_ENET_SLCR_100MBPS_DIV0;
|
|
CrlApbDiv1 = XPAR_PSU_ETHERNET_1_ENET_SLCR_100MBPS_DIV1;
|
|
#endif
|
|
} else if (mac_baseaddr == ZYNQMP_EMACPS_2_BASEADDR) {
|
|
#ifdef XPAR_PSU_ETHERNET_2_ENET_SLCR_100MBPS_DIV0
|
|
CrlApbDiv0 = XPAR_PSU_ETHERNET_2_ENET_SLCR_100MBPS_DIV0;
|
|
CrlApbDiv1 = XPAR_PSU_ETHERNET_2_ENET_SLCR_100MBPS_DIV1;
|
|
#endif
|
|
} else if (mac_baseaddr == ZYNQMP_EMACPS_3_BASEADDR) {
|
|
#ifdef XPAR_PSU_ETHERNET_3_ENET_SLCR_100MBPS_DIV0
|
|
CrlApbDiv0 = XPAR_PSU_ETHERNET_3_ENET_SLCR_100MBPS_DIV0;
|
|
CrlApbDiv1 = XPAR_PSU_ETHERNET_3_ENET_SLCR_100MBPS_DIV1;
|
|
#endif
|
|
}
|
|
} else {
|
|
if (mac_baseaddr == ZYNQMP_EMACPS_0_BASEADDR) {
|
|
#ifdef XPAR_PSU_ETHERNET_0_ENET_SLCR_10MBPS_DIV0
|
|
CrlApbDiv0 = XPAR_PSU_ETHERNET_0_ENET_SLCR_10MBPS_DIV0;
|
|
CrlApbDiv1 = XPAR_PSU_ETHERNET_0_ENET_SLCR_10MBPS_DIV1;
|
|
#endif
|
|
} else if (mac_baseaddr == ZYNQMP_EMACPS_1_BASEADDR) {
|
|
#ifdef XPAR_PSU_ETHERNET_1_ENET_SLCR_10MBPS_DIV0
|
|
CrlApbDiv0 = XPAR_PSU_ETHERNET_1_ENET_SLCR_10MBPS_DIV0;
|
|
CrlApbDiv1 = XPAR_PSU_ETHERNET_1_ENET_SLCR_10MBPS_DIV1;
|
|
#endif
|
|
} else if (mac_baseaddr == ZYNQMP_EMACPS_2_BASEADDR) {
|
|
#ifdef XPAR_PSU_ETHERNET_2_ENET_SLCR_10MBPS_DIV0
|
|
CrlApbDiv0 = XPAR_PSU_ETHERNET_2_ENET_SLCR_10MBPS_DIV0;
|
|
CrlApbDiv1 = XPAR_PSU_ETHERNET_2_ENET_SLCR_10MBPS_DIV1;
|
|
#endif
|
|
} else if (mac_baseaddr == ZYNQMP_EMACPS_3_BASEADDR) {
|
|
#ifdef XPAR_PSU_ETHERNET_3_ENET_SLCR_10MBPS_DIV0
|
|
CrlApbDiv0 = XPAR_PSU_ETHERNET_3_ENET_SLCR_10MBPS_DIV0;
|
|
CrlApbDiv1 = XPAR_PSU_ETHERNET_3_ENET_SLCR_10MBPS_DIV1;
|
|
#endif
|
|
}
|
|
}
|
|
|
|
if (CrlApbDiv0 != 0 && CrlApbDiv1 != 0) {
|
|
#if EL1_NONSECURE
|
|
XSmc_OutVar RegRead;
|
|
RegRead = Xil_Smc(MMIO_READ_SMC_FID, (u64)(CrlApbBaseAddr),
|
|
0, 0, 0, 0, 0, 0);
|
|
CrlApbGemCtrl = RegRead.Arg0 >> 32;
|
|
#else
|
|
CrlApbGemCtrl = *(volatile u32_t *)(UINTPTR)(CrlApbBaseAddr);
|
|
#endif
|
|
CrlApbGemCtrl &= ~CRL_APB_GEM_DIV0_MASK;
|
|
CrlApbGemCtrl |= CrlApbDiv0 << CRL_APB_GEM_DIV0_SHIFT;
|
|
CrlApbGemCtrl &= ~CRL_APB_GEM_DIV1_MASK;
|
|
CrlApbGemCtrl |= CrlApbDiv1 << CRL_APB_GEM_DIV1_SHIFT;
|
|
#if EL1_NONSECURE
|
|
Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(CrlApbBaseAddr) | ((u64)(0xFFFFFFFF) << 32),
|
|
(u64)CrlApbGemCtrl, 0, 0, 0, 0, 0);
|
|
do {
|
|
RegRead = Xil_Smc(MMIO_READ_SMC_FID, (u64)(CrlApbBaseAddr),
|
|
0, 0, 0, 0, 0, 0);
|
|
} while((RegRead.Arg0 >> 32) != CrlApbGemCtrl);
|
|
#else
|
|
*(volatile u32_t *)(UINTPTR)(CrlApbBaseAddr) = CrlApbGemCtrl;
|
|
#endif
|
|
} else {
|
|
xil_printf("Clock Divisors incorrect - Please check\r\n");
|
|
}
|
|
} else if (gigeversion == GEM_VERSION_VERSAL) {
|
|
/* Setup divisors in CRL for Versal */
|
|
if (mac_baseaddr == VERSAL_EMACPS_0_BASEADDR) {
|
|
CrlApbBaseAddr = VERSAL_CRL_GEM0_REF_CTRL;
|
|
#if EL1_NONSECURE
|
|
ClkId = CLK_GEM0_REF;
|
|
#endif
|
|
} else if (mac_baseaddr == VERSAL_EMACPS_1_BASEADDR) {
|
|
CrlApbBaseAddr = VERSAL_CRL_GEM1_REF_CTRL;
|
|
#if EL1_NONSECURE
|
|
ClkId = CLK_GEM1_REF;
|
|
#endif
|
|
}
|
|
|
|
if (speed == 1000) {
|
|
if (mac_baseaddr == VERSAL_EMACPS_0_BASEADDR) {
|
|
#ifdef XPAR_PSV_ETHERNET_0_ENET_SLCR_1000MBPS_DIV0
|
|
CrlApbDiv0 = XPAR_PSV_ETHERNET_0_ENET_SLCR_1000MBPS_DIV0;
|
|
#endif
|
|
} else if (mac_baseaddr == VERSAL_EMACPS_1_BASEADDR) {
|
|
#ifdef XPAR_PSV_ETHERNET_1_ENET_SLCR_1000MBPS_DIV0
|
|
CrlApbDiv0 = XPAR_PSV_ETHERNET_1_ENET_SLCR_1000MBPS_DIV0;
|
|
#endif
|
|
}
|
|
} else if (speed == 100) {
|
|
if (mac_baseaddr == VERSAL_EMACPS_0_BASEADDR) {
|
|
#ifdef XPAR_PSV_ETHERNET_0_ENET_SLCR_100MBPS_DIV0
|
|
CrlApbDiv0 = XPAR_PSV_ETHERNET_0_ENET_SLCR_100MBPS_DIV0;
|
|
#endif
|
|
} else if (mac_baseaddr == VERSAL_EMACPS_1_BASEADDR) {
|
|
#ifdef XPAR_PSV_ETHERNET_1_ENET_SLCR_100MBPS_DIV0
|
|
CrlApbDiv0 = XPAR_PSV_ETHERNET_1_ENET_SLCR_100MBPS_DIV0;
|
|
#endif
|
|
}
|
|
} else {
|
|
if (mac_baseaddr == VERSAL_EMACPS_0_BASEADDR) {
|
|
#ifdef XPAR_PSV_ETHERNET_0_ENET_SLCR_10MBPS_DIV0
|
|
CrlApbDiv0 = XPAR_PSV_ETHERNET_0_ENET_SLCR_10MBPS_DIV0;
|
|
#endif
|
|
} else if (mac_baseaddr == VERSAL_EMACPS_1_BASEADDR) {
|
|
#ifdef XPAR_PSV_ETHERNET_1_ENET_SLCR_10MBPS_DIV0
|
|
CrlApbDiv0 = XPAR_PSV_ETHERNET_1_ENET_SLCR_10MBPS_DIV0;
|
|
#endif
|
|
}
|
|
}
|
|
|
|
if (CrlApbDiv0 != 0) {
|
|
#if EL1_NONSECURE
|
|
Xil_Smc(PM_SET_DIVIDER_SMC_FID, (((u64)CrlApbDiv0 << 32) | ClkId), 0, 0, 0, 0, 0, 0);
|
|
#else
|
|
CrlApbGemCtrl = Xil_In32((UINTPTR)CrlApbBaseAddr);
|
|
CrlApbGemCtrl &= ~VERSAL_CRL_GEM_DIV_MASK;
|
|
CrlApbGemCtrl |= CrlApbDiv0 << VERSAL_CRL_APB_GEM_DIV_SHIFT;
|
|
|
|
Xil_Out32((UINTPTR)CrlApbBaseAddr, CrlApbGemCtrl);
|
|
#endif
|
|
} else {
|
|
xil_printf("Clock Divisors incorrect - Please check\r\n");
|
|
}
|
|
}
|
|
|
|
return;
|
|
}
|