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rt-thread-official/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Src/ft32f0xx_syscfg.c

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/**
******************************************************************************
* @file ft32f0xx_syscfg.c
* @author FMD AE
* @brief This file provides firmware functions to manage the following
* functionalities of the SYSCFG peripheral:
* + Remapping the memory mapped at 0x00000000
* + Remapping the DMA channels
* + Enabling I2C fast mode plus driving capability for I2C pins
* + Configuring the EXTI lines connection to the GPIO port
* + Configuring the CFGR2 features (Connecting some internal signal
* to the break input of TIM1)
* @version V1.0.0
* @data 2021-07-01
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "ft32f0xx_syscfg.h"
/**
* @brief Deinitializes the SYSCFG registers to their default reset values.
* @param None
* @retval None
* @note MEM_MODE bits are not affected by APB reset.
* @note MEM_MODE bits took the value from the user option bytes.
* @note CFGR2 register is not affected by APB reset.
* @note CLABBB configuration bits are locked when set.
* @note To unlock the configuration, perform a system reset.
*/
void SYSCFG_DeInit(void)
{
/* Set SYSCFG_CFGR1 register to reset value without affecting MEM_MODE bits */
SYSCFG->CFGR1 &= SYSCFG_CFGR1_MEM_MODE;
/* Set EXTICRx registers to reset value */
SYSCFG->EXTICR[0] = 0;
SYSCFG->EXTICR[1] = 0;
SYSCFG->EXTICR[2] = 0;
SYSCFG->EXTICR[3] = 0;
/* Set CFGR2 register to reset value: clear SRAM parity error flag */
SYSCFG->CFGR2 |= 0;
}
/**
* @brief Configures the memory mapping at address 0x00000000.
* @param SYSCFG_MemoryRemap: selects the memory remapping.
* This parameter can be one of the following values:
* @arg SYSCFG_MemoryRemap_Flash: Main Flash memory mapped at 0x00000000
* @arg SYSCFG_MemoryRemap_SystemMemory: System Flash memory mapped at 0x00000000
* @arg SYSCFG_MemoryRemap_SRAM: Embedded SRAM mapped at 0x00000000
* @retval None
*/
void SYSCFG_MemoryRemapConfig(uint32_t SYSCFG_MemoryRemap)
{
uint32_t tmpctrl = 0;
/* Check the parameter */
assert_param(IS_SYSCFG_MEMORY_REMAP(SYSCFG_MemoryRemap));
/* Get CFGR1 register value */
tmpctrl = SYSCFG->CFGR1;
/* Clear MEM_MODE bits */
tmpctrl &= (uint32_t) (~SYSCFG_CFGR1_MEM_MODE);
/* Set the new MEM_MODE bits value */
tmpctrl |= (uint32_t) SYSCFG_MemoryRemap;
/* Set CFGR1 register with the new memory remap configuration */
SYSCFG->CFGR1 = tmpctrl;
}
/**
* @brief Configure the DMA channels remapping.
* @param SYSCFG_DMARemap: selects the DMA channels remap.
* This parameter can be one of the following values:
* @arg SYSCFG_DMARemap_TIM17: Remap TIM17 DMA requests from channel1 to channel2
* @arg SYSCFG_DMARemap_TIM16: Remap TIM16 DMA requests from channel3 to channel4
* @arg SYSCFG_DMARemap_USART1Rx: Remap USART1 Rx DMA requests from channel3 to channel5
* @arg SYSCFG_DMARemap_USART1Tx: Remap USART1 Tx DMA requests from channel2 to channel4
* @arg SYSCFG_DMARemap_ADC1: Remap ADC1 DMA requests from channel1 to channel2
* @param NewState: new state of the DMA channel remapping.
* This parameter can be: ENABLE or DISABLE.
* @note When enabled, DMA channel of the selected peripheral is remapped
* @note When disabled, Default DMA channel is mapped to the selected peripheral
* @note By default TIM17 DMA requests is mapped to channel 1,
* use SYSCFG_DMAChannelRemapConfig(SYSCFG_DMARemap_TIM17, Enable) to remap
* TIM17 DMA requests to channel 2 and use
* SYSCFG_DMAChannelRemapConfig(SYSCFG_DMARemap_TIM17, Disable) to map
* TIM17 DMA requests to channel 1 (default mapping)
* @retval None
*/
void SYSCFG_DMAChannelRemapConfig(uint32_t SYSCFG_DMARemap, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_SYSCFG_DMA_REMAP(SYSCFG_DMARemap));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Remap the DMA channel */
SYSCFG->CFGR1 |= (uint32_t)SYSCFG_DMARemap;
}
else
{
/* use the default DMA channel mapping */
SYSCFG->CFGR1 &= (uint32_t)(~SYSCFG_DMARemap);
}
}
/**
* @brief Configure the I2C fast mode plus driving capability.
* @param SYSCFG_I2CFastModePlus: selects the pin.
* This parameter can be one of the following values:
* @arg SYSCFG_I2CFastModePlus_PB6: Configure fast mode plus driving capability for PB6
* @arg SYSCFG_I2CFastModePlus_PB7: Configure fast mode plus driving capability for PB7
* @arg SYSCFG_I2CFastModePlus_PB8: Configure fast mode plus driving capability for PB8
* @arg SYSCFG_I2CFastModePlus_PB9: Configure fast mode plus driving capability for PB9
* @arg SYSCFG_I2CFastModePlus_PA9: Configure fast mode plus driving capability for PA9
* @arg SYSCFG_I2CFastModePlus_PA10: Configure fast mode plus driving capability for PA10
* @arg SYSCFG_I2CFastModePlus_I2C1: Configure fast mode plus driving capability for PB10, PB11, PF6 and PF7
* @arg SYSCFG_I2CFastModePlus_I2C2: Configure fast mode plus driving capability for I2C2 pins
*
* @param NewState: new state of the DMA channel remapping.
* This parameter can be: ENABLE or DISABLE.
* @note ENABLE: Enable fast mode plus driving capability for selected I2C pin
* @note DISABLE: Disable fast mode plus driving capability for selected I2C pin
* @note For I2C1, fast mode plus driving capability can be enabled on all selected
* I2C1 pins using SYSCFG_I2CFastModePlus_I2C1 parameter or independently
* on each one of the following pins PB6, PB7, PB8 and PB9.
* @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability
* can be enabled only by using SYSCFG_I2CFastModePlus_I2C1 parameter.
* @note For all I2C2 pins fast mode plus driving capability can be enabled
* only by using SYSCFG_I2CFastModePlus_I2C2 parameter.
* @retval None
*/
void SYSCFG_I2CFastModePlusConfig(uint32_t SYSCFG_I2CFastModePlus, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_SYSCFG_I2C_FMP(SYSCFG_I2CFastModePlus));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable fast mode plus driving capability for selected pin */
SYSCFG->CFGR1 |= (uint32_t)SYSCFG_I2CFastModePlus;
}
else
{
/* Disable fast mode plus driving capability for selected pin */
SYSCFG->CFGR1 &= (uint32_t)(~SYSCFG_I2CFastModePlus);
}
}
/** @brief select the modulation envelope source
* @param SYSCFG_IRDAEnv: select the envelope source.
* This parameter can be a value
* @arg SYSCFG_IRDA_ENV_SEL_TIM16
* @arg SYSCFG_IRDA_ENV_SEL_USART1
* @arg SYSCFG_IRDA_ENV_SEL_USART2
* @retval None
*/
void SYSCFG_IRDAEnvSelection(uint32_t SYSCFG_IRDAEnv)
{
/* Check the parameters */
assert_param(IS_SYSCFG_IRDA_ENV(SYSCFG_IRDAEnv));
SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_IRDA_ENV_SEL);
SYSCFG->CFGR1 |= (SYSCFG_IRDAEnv);
}
/**
* @brief Selects the GPIO pin used as EXTI Line.
* @param EXTI_PortSourceGPIOx: selects the GPIO port to be used as source
* for EXTI lines where x can be (A, B, C, D, E or F).
* @param EXTI_PinSourcex: specifies the EXTI line to be configured.
* @note This parameter can be EXTI_PinSourcex where x can be:
* (0..15) for GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, (0..10) for GPIOF.
* @retval None
*/
void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex)
{
uint32_t tmp = 0x00;
/* Check the parameters */
assert_param(IS_EXTI_PORT_SOURCE(EXTI_PortSourceGPIOx));
assert_param(IS_EXTI_PIN_SOURCE(EXTI_PinSourcex));
tmp = ((uint32_t)0x0F) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03));
SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] &= ~tmp;
SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] |= (((uint32_t)EXTI_PortSourceGPIOx) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03)));
}
/**
* @brief Connect the selected parameter to the break input of TIM1.
* @note The selected configuration is locked and can be unlocked by system reset
* @param SYSCFG_Break: selects the configuration to be connected to break
* input of TIM1
* This parameter can be any combination of the following values:
* @arg SYSCFG_Break_PVD: Connects the PVD event to the Break Input of TIM1
* @arg SYSCFG_Break_SRAMParity: Connects the SRAM_PARITY error signal to the Break Input of TIM1 .
* @arg SYSCFG_Break_Lockup: Connects Lockup output of CortexM0 to the break input of TIM1.
* @retval None
*/
void SYSCFG_BreakConfig(uint32_t SYSCFG_Break)
{
/* Check the parameter */
assert_param(IS_SYSCFG_LOCK_CONFIG(SYSCFG_Break));
SYSCFG->CFGR2 |= (uint32_t) SYSCFG_Break;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT FMD *****END OF FILE****/
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