829 lines
24 KiB
C
829 lines
24 KiB
C
/**
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* \file
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*
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* \brief SAM UART Driver for SAMB11
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*
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* Copyright (C) 2015-2016 Atmel Corporation. All rights reserved.
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*
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* \asf_license_start
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*
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* \page License
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. The name of Atmel may not be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* 4. This software may only be redistributed and used in connection with an
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* Atmel microcontroller product.
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*
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* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* \asf_license_stop
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*
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*/
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/*
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* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
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*/
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#include "uart.h"
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/**
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* \internal
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* Internal driver device instance struct.
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*/
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struct uart_module *_uart_instances[UART_INST_NUM];
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/**
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* \internal
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* Writes a character from the TX buffer to the Data register.
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*
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* \param[in,out] module Pointer to UART software instance struct
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*/
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static void _uart_write(struct uart_module *const module)
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{
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/* Pointer to the hardware module instance */
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Uart *const uart_hw = module->hw;
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/* Write value will be at least 8-bits long */
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uint8_t data_to_send = *(module->tx_buffer_ptr);
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/* Increment 8-bit pointer */
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(module->tx_buffer_ptr)++;
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/* Write the data to send*/
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uart_hw->TRANSMIT_DATA.reg = data_to_send & UART_TRANSMIT_DATA_MASK;
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/* Decrement remaining buffer length */
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(module->remaining_tx_buffer_length)--;
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}
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/**
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* \internal
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* Reads a character from the Data register to the RX buffer.
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*
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* \param[in,out] module Pointer to UART software instance struct
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*/
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static void _uart_read(
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struct uart_module *const module)
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{
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/* Pointer to the hardware module instance */
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Uart *const uart_hw = module->hw;
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uint16_t received_data = (uart_hw->RECEIVE_DATA.reg & UART_RECEIVE_DATA_MASK);
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/* Read value will be at least 8-bits long */
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*(module->rx_buffer_ptr) = received_data;
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/* Increment 8-bit pointer */
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module->rx_buffer_ptr += 1;
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/* Decrement length of the remaining buffer */
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module->remaining_rx_buffer_length--;
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}
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static void uart_rx0_isr_handler(void)
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{
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struct uart_module *module = _uart_instances[0];
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/* get interrupt flags and mask out enabled callbacks */
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uint32_t flags = module->hw->RECEIVE_STATUS.reg;
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if (flags & UART_RECEIVE_STATUS_FIFO_OVERRUN) {
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/* Store the error code */
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module->status = STATUS_ERR_OVERFLOW;
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/* Disable interrupt */
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module->hw->RX_INTERRUPT_MASK.reg &=
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~(UART_RX_INTERRUPT_MASK_FIFO_OVERRUN_MASK |
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SPI_RX_INTERRUPT_MASK_RX_FIFO_NOT_EMPTY_MASK);
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if ((module->callback_enable_mask & (1 << UART_RX_FIFO_OVERRUN)) &&
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(module->callback_reg_mask & (1 << UART_RX_FIFO_OVERRUN))) {
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(module->callback[UART_RX_FIFO_OVERRUN])(module);
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}
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/* Flush */
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uint8_t flush = module->hw->RECEIVE_DATA.reg;
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UNUSED(flush);
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}
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if (flags & UART_RECEIVE_STATUS_RX_FIFO_NOT_EMPTY) {
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_uart_read(module);
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if (module->remaining_rx_buffer_length == 0) {
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if ((module->callback_enable_mask & (1 << UART_RX_COMPLETE)) &&
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(module->callback_reg_mask & (1 << UART_RX_COMPLETE))) {
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module->status = STATUS_OK;
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module->hw->RX_INTERRUPT_MASK.reg &=
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~(UART_RX_INTERRUPT_MASK_RX_FIFO_NOT_EMPTY_MASK);
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(module->callback[UART_RX_COMPLETE])(module);
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}
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}
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}
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}
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static void uart_tx0_isr_handler(void)
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{
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struct uart_module *module = _uart_instances[0];
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/* get interrupt flags and mask out enabled callbacks */
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uint32_t flags = module->hw->TRANSMIT_STATUS.reg;
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if (flags & UART_TRANSMIT_STATUS_TX_FIFO_NOT_FULL) {
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_uart_write(module);
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if (module->remaining_tx_buffer_length == 0) {
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module->hw->TX_INTERRUPT_MASK.reg &=
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~UART_TX_INTERRUPT_MASK_TX_FIFO_NOT_FULL_MASK;
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module->hw->TX_INTERRUPT_MASK.reg |=
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UART_TX_INTERRUPT_MASK_TX_FIFO_EMPTY_MASK;
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}
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}
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if (flags & UART_TRANSMIT_STATUS_TX_FIFO_EMPTY) {
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if ((module->callback_enable_mask & (1 << UART_TX_COMPLETE)) &&
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(module->callback_reg_mask & (1 << UART_TX_COMPLETE))) {
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module->status = STATUS_OK;
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/* Disable interrupt */
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module->hw->TX_INTERRUPT_MASK.reg &=
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~UART_TX_INTERRUPT_MASK_TX_FIFO_EMPTY_MASK;
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(module->callback[UART_TX_COMPLETE])(module);
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}
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}
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if (flags & UART_TRANSMIT_STATUS_CTS_ACTIVE) {
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if ((module->callback_enable_mask & (1 << UART_CTS_ACTIVE)) &&
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(module->callback_reg_mask & (1 << UART_CTS_ACTIVE))) {
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(module->callback[UART_CTS_ACTIVE])(module);
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}
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}
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}
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static void uart_rx1_isr_handler(void)
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{
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struct uart_module *module = _uart_instances[1];
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/* get interrupt flags and mask out enabled callbacks */
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uint32_t flags = module->hw->RECEIVE_STATUS.reg;
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if (flags & UART_RECEIVE_STATUS_FIFO_OVERRUN) {
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/* Store the error code */
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module->status = STATUS_ERR_OVERFLOW;
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/* Disable interrupt */
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module->hw->RX_INTERRUPT_MASK.reg &=
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~(UART_RX_INTERRUPT_MASK_FIFO_OVERRUN_MASK |
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SPI_RX_INTERRUPT_MASK_RX_FIFO_NOT_EMPTY_MASK);
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if ((module->callback_enable_mask & (1 << UART_RX_FIFO_OVERRUN)) &&
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(module->callback_reg_mask & (1 << UART_RX_FIFO_OVERRUN))) {
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(module->callback[UART_RX_FIFO_OVERRUN])(module);
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}
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/* Flush */
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uint8_t flush = module->hw->RECEIVE_DATA.reg;
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UNUSED(flush);
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}
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if (flags & UART_RECEIVE_STATUS_RX_FIFO_NOT_EMPTY) {
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_uart_read(module);
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if (module->remaining_rx_buffer_length == 0) {
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if ((module->callback_enable_mask & (1 << UART_RX_COMPLETE)) &&
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(module->callback_reg_mask & (1 << UART_RX_COMPLETE))) {
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module->status = STATUS_OK;
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module->hw->RX_INTERRUPT_MASK.reg &=
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~(UART_RX_INTERRUPT_MASK_RX_FIFO_NOT_EMPTY_MASK);
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(module->callback[UART_RX_COMPLETE])(module);
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}
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}
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}
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}
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static void uart_tx1_isr_handler(void)
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{
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struct uart_module *module = _uart_instances[1];
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/* get interrupt flags and mask out enabled callbacks */
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uint32_t flags = module->hw->TRANSMIT_STATUS.reg;
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if (flags & UART_TRANSMIT_STATUS_TX_FIFO_NOT_FULL) {
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_uart_write(module);
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if (module->remaining_tx_buffer_length == 0) {
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module->hw->TX_INTERRUPT_MASK.reg &=
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~UART_TX_INTERRUPT_MASK_TX_FIFO_NOT_FULL_MASK;
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module->hw->TX_INTERRUPT_MASK.reg |=
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UART_TX_INTERRUPT_MASK_TX_FIFO_EMPTY_MASK;
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}
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}
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if (flags & UART_TRANSMIT_STATUS_TX_FIFO_EMPTY) {
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if ((module->callback_enable_mask & (1 << UART_TX_COMPLETE)) &&
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(module->callback_reg_mask & (1 << UART_TX_COMPLETE))) {
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module->status = STATUS_OK;
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/* Disable interrupt */
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module->hw->TX_INTERRUPT_MASK.reg &=
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~UART_TX_INTERRUPT_MASK_TX_FIFO_EMPTY_MASK;
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(module->callback[UART_TX_COMPLETE])(module);
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}
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}
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if (flags & UART_TRANSMIT_STATUS_CTS_ACTIVE) {
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if ((module->callback_enable_mask & (1 << UART_CTS_ACTIVE)) &&
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(module->callback_reg_mask & (1 << UART_CTS_ACTIVE))) {
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(module->callback[UART_CTS_ACTIVE])(module);
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}
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}
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}
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static void uart_set_baudrate(struct uart_module *const module,
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const uint32_t baud_rate)
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{
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uint32_t clock;
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uint16_t integerpart = 0;
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uint8_t fractionalpart = 0;
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uint32_t diff;
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uint8_t i = 0;
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clock = system_clock_get_value();
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integerpart = clock / baud_rate;
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diff = clock - (baud_rate * integerpart);
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i = 0;
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while(diff > (baud_rate / 16)) {
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i++;
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diff -= (baud_rate / 16);
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}
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fractionalpart = (i + 1) / 2;
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module->hw->UART_CLOCK_SOURCE.reg = UART_CLOCK_SOURCE_CLOCK_SELECT_0;
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module->hw->UART_BAUD_RATE.reg =
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UART_BAUD_RATE_INTEGER_DIVISION(integerpart) |
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UART_BAUD_RATE_FRACTIONAL_DIVISION(fractionalpart);
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}
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/**
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* \brief Gets the UART default configurations
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*
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* Use to initialize the configuration structure to known default values.
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*
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* The default configuration is as follows:
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* - Baudrate 115200
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* - parity UART_NO_PARITY
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* - flow_control 0 - No Flow control
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* - stop_bits 1 - 1 stop bit
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* - pinmux_pad[] - Pinmux default are UART0.
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*
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* \param[out] config Pointer to configuration structure to be initiated
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*/
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void uart_get_config_defaults(
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struct uart_config *const config)
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{
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config->baud_rate = 115200;
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config->data_bits = UART_8_BITS;
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config->stop_bits = UART_1_STOP_BIT;
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config->parity = UART_NO_PARITY;
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config->flow_control = false;
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config->pin_number_pad[0] = PIN_LP_GPIO_2;
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config->pin_number_pad[1] = PIN_LP_GPIO_3;
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config->pin_number_pad[2] = PIN_LP_GPIO_4;
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config->pin_number_pad[3] = PIN_LP_GPIO_5;
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config->pinmux_sel_pad[0] = MUX_LP_GPIO_2_UART0_RXD;
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config->pinmux_sel_pad[1] = MUX_LP_GPIO_3_UART0_TXD;
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config->pinmux_sel_pad[2] = MUX_LP_GPIO_4_UART0_CTS;
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config->pinmux_sel_pad[3] = MUX_LP_GPIO_5_UART0_RTS;
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}
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/**
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* \brief Initializes the device
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*
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* Initializes the UART device based on the setting specified in the
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* configuration struct.
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*
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* \param[in] module enumeration UART hw module
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* \param[in] hw Pointer to USART hardware instance
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* \param[in] config Pointer to configuration struct
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*
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* \return Status of the initialization.
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*
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* \retval STATUS_OK The initialization was successful
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*/
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enum status_code uart_init(struct uart_module *const module, Uart * const hw,
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const struct uart_config *const config)
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{
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/* Sanity check arguments */
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Assert(module);
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Assert(hw);
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Assert(config);
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uint8_t config_temp = 0;
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uint8_t i,index;
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/* Assign module pointer to software instance struct */
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module->hw = hw;
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for (i = 0; i < UART_CALLBACK_N; i++) {
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module->callback[i] = NULL;
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}
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module->rx_buffer_ptr = NULL;
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module->tx_buffer_ptr = NULL;
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module->remaining_rx_buffer_length = 0;
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module->remaining_tx_buffer_length = 0;
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module->callback_reg_mask = 0;
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module->callback_enable_mask = 0;
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module->status = STATUS_OK;
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if (hw == UART0) {
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system_peripheral_reset(PERIPHERAL_UART0_CORE);
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system_peripheral_reset(PERIPHERAL_UART0_IF);
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system_clock_peripheral_enable(PERIPHERAL_UART0_CORE);
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system_clock_peripheral_enable(PERIPHERAL_UART0_IF);
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_uart_instances[0] = module;
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system_register_isr(RAM_ISR_TABLE_UARTRX0_INDEX, (uint32_t)uart_rx0_isr_handler);
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system_register_isr(RAM_ISR_TABLE_UARTTX0_INDEX, (uint32_t)uart_tx0_isr_handler);
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NVIC_EnableIRQ(UART0_RX_IRQn);
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NVIC_EnableIRQ(UART0_TX_IRQn);
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} else if (hw == UART1) {
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system_peripheral_reset(PERIPHERAL_UART1_CORE);
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system_peripheral_reset(PERIPHERAL_UART1_IF);
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system_clock_peripheral_enable(PERIPHERAL_UART1_CORE);
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system_clock_peripheral_enable(PERIPHERAL_UART1_IF);
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_uart_instances[1] = module;
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system_register_isr(RAM_ISR_TABLE_UARTRX1_INDEX, (uint32_t)uart_rx1_isr_handler);
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system_register_isr(RAM_ISR_TABLE_UARTTX1_INDEX, (uint32_t)uart_tx1_isr_handler);
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NVIC_EnableIRQ(UART1_RX_IRQn);
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NVIC_EnableIRQ(UART1_TX_IRQn);
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}
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/* Set the pinmux for this UART module. */
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if(config->flow_control) {
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index = 4;
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} else {
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index = 2;
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}
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#if (BTLC1000)
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index = 2; /* BTLC1000 has no flow control function. */
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#endif
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for(i = 0; i < index; i++) {
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gpio_pinmux_cofiguration(config->pin_number_pad[i], \
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(uint16_t)(config->pinmux_sel_pad[i]));
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}
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/* empty UART FIFO */
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while (module->hw->RECEIVE_STATUS.reg & UART_RECEIVE_STATUS_RX_FIFO_NOT_EMPTY) {
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i = module->hw->RECEIVE_DATA.reg;
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}
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/* reset configuration register */
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module->hw->UART_CONFIGURATION.reg = 0;
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/* program the uart configuration. */
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if(config->flow_control) {
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config_temp |= UART_CONFIGURATION_CTS_ENABLE_1;
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}
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config_temp |= config->data_bits;
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config_temp |= config->stop_bits;
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switch(config->parity) {
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case UART_NO_PARITY:
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config_temp |= UART_CONFIGURATION_PARITY_ENABLE_0;
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break;
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case UART_EVEN_PARITY:
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config_temp |= UART_CONFIGURATION_PARITY_ENABLE_1;
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config_temp |= UART_CONFIGURATION_PARITY_MODE_0;
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break;
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case UART_ODD_PARITY:
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config_temp |= UART_CONFIGURATION_PARITY_ENABLE_1;
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config_temp |= UART_CONFIGURATION_PARITY_MODE_1;
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break;
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case UART_SPACE_PARITY:
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config_temp |= UART_CONFIGURATION_PARITY_ENABLE_1;
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config_temp |= UART_CONFIGURATION_PARITY_MODE_2;
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break;
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case UART_MARK_PARITY:
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config_temp |= UART_CONFIGURATION_PARITY_ENABLE_1;
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config_temp |= UART_CONFIGURATION_PARITY_MODE_3;
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break;
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default:
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break;
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}
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module->hw->UART_CONFIGURATION.reg = config_temp;
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/* Calculate the baud rate. */
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uart_set_baudrate(module, config->baud_rate);
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module->hw->RX_INTERRUPT_MASK.reg = 0; // disable int at initialization, enable it at read time
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module->hw->TX_INTERRUPT_MASK.reg = 0; // disable int at initialization, enable it at write time
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return STATUS_OK;
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}
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/**
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* \brief Transmit a character via the UART
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*
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* This blocking function will transmit a single character via the
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* UART.
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*
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* \param[in] module enumeration UART hw module
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* \param[in] tx_data Data to transfer
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*
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* \return Status of the operation.
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* \retval STATUS_OK If the operation was completed
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*/
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enum status_code uart_write_wait(struct uart_module *const module,
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const uint8_t tx_data)
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{
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while (!(module->hw->TRANSMIT_STATUS.reg & UART_TRANSMIT_STATUS_TX_FIFO_NOT_FULL));
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module->hw->TRANSMIT_DATA.reg = tx_data;
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return STATUS_OK;
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}
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/**
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* \brief Receive a character via the UART
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*
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* This blocking function will receive a character via the UART.
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*
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* \param[in] module enumeration UART hw module
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* \param[out] rx_data Pointer to received data
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*
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* \return Status of the operation.
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* \retval STATUS_OK If the operation was completed
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*/
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enum status_code uart_read_wait(struct uart_module *const module,
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uint8_t *const rx_data)
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{
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while (!(module->hw->RECEIVE_STATUS.reg & UART_RECEIVE_STATUS_RX_FIFO_NOT_EMPTY));
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*rx_data = module->hw->RECEIVE_DATA.reg;
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return STATUS_OK;
|
|
}
|
|
|
|
/**
|
|
* \brief Transmit a buffer of characters via the UART
|
|
*
|
|
* This blocking function will transmit a block of \c length characters
|
|
* via the UART.
|
|
*
|
|
* \note Using this function in combination with the interrupt (\c _job) functions is
|
|
* not recommended as it has no functionality to check if there is an
|
|
* ongoing interrupt driven operation running or not.
|
|
*
|
|
* \param[in] module enumeration UART hw module
|
|
* \param[in] tx_data Pointer to data to transmit
|
|
* \param[in] length Number of characters to transmit
|
|
*
|
|
* \return Status of the operation.
|
|
* \retval STATUS_OK If operation was completed
|
|
*/
|
|
enum status_code uart_write_buffer_wait(struct uart_module *const module,
|
|
const uint8_t *tx_data, uint32_t length)
|
|
{
|
|
while(length--)
|
|
uart_write_wait(module, *tx_data++);
|
|
|
|
return STATUS_OK;
|
|
}
|
|
|
|
/**
|
|
* \brief Receive a buffer of \c length characters via the UART
|
|
*
|
|
* This blocking function will receive a block of \c length characters
|
|
* via the UART.
|
|
*
|
|
* \note Using this function in combination with the interrupt (\c *_job)
|
|
* functions is not recommended as it has no functionality to check if
|
|
* there is an ongoing interrupt driven operation running or not.
|
|
*
|
|
* \param[in] module enumeration UART hw module
|
|
* \param[out] rx_data Pointer to receive buffer
|
|
* \param[in] length Number of characters to receive
|
|
*
|
|
* \return Status of the operation.
|
|
* \retval STATUS_OK If operation was completed
|
|
*/
|
|
enum status_code uart_read_buffer_wait(struct uart_module *const module,
|
|
uint8_t *rx_data, uint16_t length)
|
|
{
|
|
while(length--)
|
|
uart_read_wait(module, rx_data++);
|
|
|
|
return STATUS_OK;
|
|
}
|
|
|
|
/**
|
|
* \internal
|
|
* Starts write of a buffer with a given length
|
|
*
|
|
* \param[in] module Pointer to UART software instance struct
|
|
* \param[in] tx_data Pointer to data to be transmitted
|
|
* \param[in] length Length of data buffer
|
|
*
|
|
*/
|
|
static void _uart_write_buffer(
|
|
struct uart_module *const module,
|
|
uint8_t *tx_data,
|
|
uint16_t length)
|
|
{
|
|
Assert(module);
|
|
Assert(tx_data);
|
|
|
|
/* Write parameters to the device instance */
|
|
module->remaining_tx_buffer_length = length;
|
|
module->tx_buffer_ptr = tx_data;
|
|
module->status = STATUS_BUSY;
|
|
|
|
module->hw->TX_INTERRUPT_MASK.reg = UART_TX_INTERRUPT_MASK_TX_FIFO_NOT_FULL_MASK;
|
|
}
|
|
|
|
/**
|
|
* \internal
|
|
* Setup UART to read a buffer with a given length
|
|
*
|
|
* \param[in] module Pointer to UART software instance struct
|
|
* \param[in] rx_data Pointer to data to be received
|
|
* \param[in] length Length of data buffer
|
|
*
|
|
*/
|
|
static void _uart_read_buffer(
|
|
struct uart_module *const module,
|
|
uint8_t *rx_data,
|
|
uint16_t length)
|
|
{
|
|
Assert(module);
|
|
Assert(rx_data);
|
|
|
|
/* Set length for the buffer and the pointer, and let
|
|
* the interrupt handler do the rest */
|
|
module->remaining_rx_buffer_length = length;
|
|
module->rx_buffer_ptr = rx_data;
|
|
module->status = STATUS_BUSY;
|
|
|
|
module->hw->RX_INTERRUPT_MASK.reg = UART_RX_INTERRUPT_MASK_RX_FIFO_NOT_EMPTY_MASK;
|
|
}
|
|
|
|
/**
|
|
* \brief Asynchronous buffer write
|
|
*
|
|
* Sets up the driver to write to the UART from a given buffer. If registered
|
|
* and enabled, a callback function will be called when the write is finished.
|
|
*
|
|
* \param[in] module Pointer to UART software instance struct
|
|
* \param[out] tx_data Pointer to data buffer to receive
|
|
* \param[in] length Data buffer length
|
|
*
|
|
* \returns Status of the write request operation.
|
|
* \retval STATUS_OK If the operation completed successfully
|
|
* \retval STATUS_ERR_BUSY If the UART was already busy with a write
|
|
* operation
|
|
* \retval STATUS_ERR_INVALID_ARG If requested write length was zero
|
|
*/
|
|
enum status_code uart_write_buffer_job(struct uart_module *const module,
|
|
uint8_t *tx_data, uint32_t length)
|
|
{
|
|
Assert(module);
|
|
Assert(tx_data);
|
|
|
|
if (length == 0) {
|
|
return STATUS_ERR_INVALID_ARG;
|
|
}
|
|
|
|
/* Check if the UART is busy transmitting or slave waiting for TXC*/
|
|
if (module->status == STATUS_BUSY) {
|
|
return STATUS_BUSY;
|
|
}
|
|
|
|
/* Issue internal write */
|
|
_uart_write_buffer(module, tx_data, length);
|
|
|
|
return STATUS_OK;
|
|
}
|
|
|
|
/**
|
|
* \brief Asynchronous buffer read
|
|
*
|
|
* Sets up the driver to read from the UART to a given buffer. If registered
|
|
* and enabled, a callback function will be called when the read is finished.
|
|
*
|
|
* \note If address matching is enabled for the slave, the first character
|
|
* received and placed in the RX buffer will be the address.
|
|
*
|
|
* \param[in] module Pointer to UART software instance struct
|
|
* \param[out] rx_data Pointer to data buffer to receive
|
|
* \param[in] length Data buffer length
|
|
* \param[in] dummy Dummy character to send when reading in master mode
|
|
*
|
|
* \returns Status of the operation.
|
|
* \retval STATUS_OK If the operation completed successfully
|
|
* \retval STATUS_ERR_BUSY If the UART was already busy with a read
|
|
* operation
|
|
* \retval STATUS_ERR_DENIED If the receiver is not enabled
|
|
* \retval STATUS_ERR_INVALID_ARG If requested read length was zero
|
|
*/
|
|
enum status_code uart_read_buffer_job(struct uart_module *const module,
|
|
uint8_t *rx_data, uint16_t length)
|
|
{
|
|
/* Sanity check arguments */
|
|
Assert(module);
|
|
Assert(rx_data);
|
|
|
|
if (length == 0) {
|
|
return STATUS_ERR_INVALID_ARG;
|
|
}
|
|
|
|
/* Check if the UART is busy transmitting or slave waiting for TXC*/
|
|
if (module->status == STATUS_BUSY) {
|
|
return STATUS_BUSY;
|
|
}
|
|
|
|
/* Issue internal read */
|
|
_uart_read_buffer(module, rx_data, length);
|
|
return STATUS_OK;
|
|
}
|
|
|
|
/**
|
|
* \brief Registers a callback
|
|
*
|
|
* Registers a callback function which is implemented by the user.
|
|
*
|
|
* \note The callback must be enabled by \ref uart_enable_callback,
|
|
* in order for the interrupt handler to call it when the conditions for
|
|
* the callback type are met.
|
|
*
|
|
* \param[in] module Pointer to UART software instance struct
|
|
* \param[in] callback_func Pointer to callback function
|
|
* \param[in] callback_type Callback type given by an enum
|
|
*
|
|
*/
|
|
void uart_register_callback(struct uart_module *const module,
|
|
uart_callback_t callback_func,
|
|
enum uart_callback callback_type)
|
|
{
|
|
/* Sanity check arguments */
|
|
Assert(module);
|
|
Assert(callback_func);
|
|
|
|
/* Register callback function */
|
|
module->callback[callback_type] = callback_func;
|
|
/* Set the bit corresponding to the callback_type */
|
|
module->callback_reg_mask |= (1 << callback_type);
|
|
}
|
|
|
|
/**
|
|
* \brief Unregisters a callback
|
|
*
|
|
* Unregisters a callback function which is implemented by the user.
|
|
*
|
|
* \param[in,out] module Pointer to UART software instance struct
|
|
* \param[in] callback_type Callback type given by an enum
|
|
*
|
|
*/
|
|
void uart_unregister_callback(struct uart_module *module,
|
|
enum uart_callback callback_type)
|
|
{
|
|
/* Sanity check arguments */
|
|
Assert(module);
|
|
|
|
/* Unregister callback function */
|
|
module->callback[callback_type] = NULL;
|
|
/* Clear the bit corresponding to the callback_type */
|
|
module->callback_reg_mask &= ~(1 << callback_type);
|
|
}
|
|
|
|
/**
|
|
* \brief Enables callback
|
|
*
|
|
* Enables the callback function registered by the \ref usart_register_callback.
|
|
* The callback function will be called from the interrupt handler when the
|
|
* conditions for the callback type are met.
|
|
*
|
|
* \param[in] module Pointer to UART software instance struct
|
|
* \param[in] callback_type Callback type given by an enum
|
|
*/
|
|
void uart_enable_callback(struct uart_module *const module,
|
|
enum uart_callback callback_type)
|
|
{
|
|
/* Sanity check arguments */
|
|
Assert(module);
|
|
|
|
/* Enable callback */
|
|
module->callback_enable_mask |= (1 << callback_type);
|
|
|
|
if (callback_type == UART_CTS_ACTIVE) {
|
|
module->hw->TX_INTERRUPT_MASK.reg |= UART_TX_INTERRUPT_MASK_CTS_ACTIVE_MASK;
|
|
}
|
|
}
|
|
|
|
/**
|
|
* \brief Disable callback
|
|
*
|
|
* Disables the callback function registered by the \ref usart_register_callback,
|
|
* and the callback will not be called from the interrupt routine.
|
|
*
|
|
* \param[in] module Pointer to UART software instance struct
|
|
* \param[in] callback_type Callback type given by an enum
|
|
*/
|
|
void uart_disable_callback(struct uart_module *const module,
|
|
enum uart_callback callback_type)
|
|
{
|
|
/* Sanity check arguments */
|
|
Assert(module);
|
|
|
|
/* Disable callback */
|
|
module->callback_enable_mask &= ~(1 << callback_type);
|
|
|
|
if (callback_type == UART_CTS_ACTIVE) {
|
|
module->hw->TX_INTERRUPT_MASK.reg &= ~UART_TX_INTERRUPT_MASK_CTS_ACTIVE_MASK;
|
|
}
|
|
|
|
}
|
|
|
|
/**
|
|
* \brief Enables UART transmit DMA
|
|
*
|
|
* \param[in] module Pointer to UART software instance struct
|
|
*/
|
|
void uart_enable_transmit_dma(struct uart_module *const module)
|
|
{
|
|
/* Sanity check arguments */
|
|
Assert(module);
|
|
|
|
/* DMA need the interrupt signal to trigger */
|
|
module->hw->TX_INTERRUPT_MASK.reg |= UART_TX_INTERRUPT_MASK_TX_FIFO_EMPTY_MASK;
|
|
|
|
/* Disable NVIC to avoid trigger the CPU interrupt */
|
|
if (module->hw == UART0) {
|
|
NVIC_DisableIRQ(UART0_TX_IRQn);
|
|
} else if (module->hw == UART1) {
|
|
NVIC_DisableIRQ(UART1_TX_IRQn);
|
|
}
|
|
}
|
|
|
|
/**
|
|
* \brief Disables UART transmit DMA
|
|
*
|
|
* \param[in] module Pointer to UART software instance struct
|
|
*/
|
|
void uart_disable_transmit_dma(struct uart_module *const module)
|
|
{
|
|
/* Sanity check arguments */
|
|
Assert(module);
|
|
|
|
module->hw->TX_INTERRUPT_MASK.reg &= ~UART_TX_INTERRUPT_MASK_TX_FIFO_EMPTY_MASK;
|
|
|
|
/* Enable NVIC to restore the callback functions */
|
|
if (module->hw == UART0) {
|
|
NVIC_EnableIRQ(UART0_TX_IRQn);
|
|
} else if (module->hw == UART1) {
|
|
NVIC_EnableIRQ(UART1_TX_IRQn);
|
|
}
|
|
}
|
|
|
|
/**
|
|
* \brief Enables UART receive DMA
|
|
*
|
|
* \param[in] module Pointer to UART software instance struct
|
|
*/
|
|
void uart_enable_receive_dma(struct uart_module *const module)
|
|
{
|
|
/* Sanity check arguments */
|
|
Assert(module);
|
|
|
|
/* DMA need the interrupt signal to trigger */
|
|
module->hw->RX_INTERRUPT_MASK.reg |= UART_RX_INTERRUPT_MASK_RX_FIFO_NOT_EMPTY_MASK;
|
|
|
|
/* Disable NVIC to avoid trigger the CPU interrupt */
|
|
if (module->hw == UART0) {
|
|
NVIC_DisableIRQ(UART0_TX_IRQn);
|
|
} else if (module->hw == UART1) {
|
|
NVIC_DisableIRQ(UART1_TX_IRQn);
|
|
}
|
|
}
|
|
|
|
/**
|
|
* \brief Disables UART receive DMA
|
|
*
|
|
* \param[in] module Pointer to UART software instance struct
|
|
*/
|
|
void uart_disable_receive_dma(struct uart_module *const module)
|
|
{
|
|
/* Sanity check arguments */
|
|
Assert(module);
|
|
|
|
module->hw->RX_INTERRUPT_MASK.reg &= ~UART_RX_INTERRUPT_MASK_RX_FIFO_NOT_EMPTY_MASK;
|
|
|
|
/* Enable NVIC to restore the callback functions */
|
|
if (module->hw == UART0) {
|
|
NVIC_EnableIRQ(UART0_TX_IRQn);
|
|
} else if (module->hw == UART1) {
|
|
NVIC_EnableIRQ(UART1_TX_IRQn);
|
|
}
|
|
}
|
|
|