188 lines
5.7 KiB
C
188 lines
5.7 KiB
C
/*
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* Copyright (c) 2006-2020, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2011-09-15 Bernard first version
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*/
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#ifndef __ARMV8_H__
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#define __ARMV8_H__
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#include <rtconfig.h>
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#ifdef ARCH_USING_HW_THREAD_SELF
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#define ARM64_THREAD_REG tpidr_el1
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#endif /* ARCH_USING_HW_THREAD_SELF */
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#ifdef __ASSEMBLY__
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/*********************
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* CONTEXT_OFFSET *
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*********************/
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#define CONTEXT_OFFSET_ELR_EL1 0x0
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#define CONTEXT_OFFSET_SPSR_EL1 0x8
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#define CONTEXT_OFFSET_SP_EL0 0x10
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#define CONTEXT_OFFSET_X30 0x18
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#define CONTEXT_OFFSET_FPCR 0x20
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#define CONTEXT_OFFSET_FPSR 0x28
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#define CONTEXT_OFFSET_X28 0x30
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#define CONTEXT_OFFSET_X29 0x38
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#define CONTEXT_OFFSET_X26 0x40
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#define CONTEXT_OFFSET_X27 0x48
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#define CONTEXT_OFFSET_X24 0x50
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#define CONTEXT_OFFSET_X25 0x58
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#define CONTEXT_OFFSET_X22 0x60
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#define CONTEXT_OFFSET_X23 0x68
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#define CONTEXT_OFFSET_X20 0x70
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#define CONTEXT_OFFSET_X21 0x78
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#define CONTEXT_OFFSET_X18 0x80
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#define CONTEXT_OFFSET_X19 0x88
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#define CONTEXT_OFFSET_X16 0x90
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#define CONTEXT_OFFSET_X17 0x98
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#define CONTEXT_OFFSET_X14 0xa0
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#define CONTEXT_OFFSET_X15 0xa8
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#define CONTEXT_OFFSET_X12 0xb0
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#define CONTEXT_OFFSET_X13 0xb8
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#define CONTEXT_OFFSET_X10 0xc0
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#define CONTEXT_OFFSET_X11 0xc8
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#define CONTEXT_OFFSET_X8 0xd0
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#define CONTEXT_OFFSET_X9 0xd8
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#define CONTEXT_OFFSET_X6 0xe0
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#define CONTEXT_OFFSET_X7 0xe8
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#define CONTEXT_OFFSET_X4 0xf0
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#define CONTEXT_OFFSET_X5 0xf8
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#define CONTEXT_OFFSET_X2 0x100
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#define CONTEXT_OFFSET_X3 0x108
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#define CONTEXT_OFFSET_X0 0x110
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#define CONTEXT_OFFSET_X1 0x118
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#define CONTEXT_OFFSET_Q31 0x120
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#define CONTEXT_OFFSET_Q30 0x130
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#define CONTEXT_OFFSET_Q29 0x140
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#define CONTEXT_OFFSET_Q28 0x150
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#define CONTEXT_OFFSET_Q27 0x160
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#define CONTEXT_OFFSET_Q26 0x170
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#define CONTEXT_OFFSET_Q25 0x180
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#define CONTEXT_OFFSET_Q24 0x190
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#define CONTEXT_OFFSET_Q23 0x1a0
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#define CONTEXT_OFFSET_Q22 0x1b0
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#define CONTEXT_OFFSET_Q21 0x1c0
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#define CONTEXT_OFFSET_Q20 0x1d0
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#define CONTEXT_OFFSET_Q19 0x1e0
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#define CONTEXT_OFFSET_Q18 0x1f0
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#define CONTEXT_OFFSET_Q17 0x200
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#define CONTEXT_OFFSET_Q16 0x210
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#define CONTEXT_OFFSET_Q15 0x220
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#define CONTEXT_OFFSET_Q14 0x230
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#define CONTEXT_OFFSET_Q13 0x240
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#define CONTEXT_OFFSET_Q12 0x250
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#define CONTEXT_OFFSET_Q11 0x260
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#define CONTEXT_OFFSET_Q10 0x270
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#define CONTEXT_OFFSET_Q9 0x280
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#define CONTEXT_OFFSET_Q8 0x290
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#define CONTEXT_OFFSET_Q7 0x2a0
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#define CONTEXT_OFFSET_Q6 0x2b0
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#define CONTEXT_OFFSET_Q5 0x2c0
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#define CONTEXT_OFFSET_Q4 0x2d0
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#define CONTEXT_OFFSET_Q3 0x2e0
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#define CONTEXT_OFFSET_Q2 0x2f0
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#define CONTEXT_OFFSET_Q1 0x300
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#define CONTEXT_OFFSET_Q0 0x310
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#define CONTEXT_FPU_SIZE (32 * 16)
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#define CONTEXT_SIZE (0x120 + CONTEXT_FPU_SIZE)
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#else /* !__ASSEMBLY__ */
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#include <rttypes.h>
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typedef struct { rt_uint64_t value[2]; } rt_uint128_t;
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/* the exception stack without VFP registers */
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struct rt_hw_exp_stack
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{
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rt_uint64_t pc;
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rt_uint64_t cpsr;
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rt_uint64_t sp_el0;
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rt_uint64_t x30;
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rt_uint64_t fpcr;
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rt_uint64_t fpsr;
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rt_uint64_t x28;
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rt_uint64_t x29;
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rt_uint64_t x26;
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rt_uint64_t x27;
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rt_uint64_t x24;
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rt_uint64_t x25;
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rt_uint64_t x22;
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rt_uint64_t x23;
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rt_uint64_t x20;
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rt_uint64_t x21;
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rt_uint64_t x18;
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rt_uint64_t x19;
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rt_uint64_t x16;
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rt_uint64_t x17;
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rt_uint64_t x14;
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rt_uint64_t x15;
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rt_uint64_t x12;
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rt_uint64_t x13;
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rt_uint64_t x10;
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rt_uint64_t x11;
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rt_uint64_t x8;
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rt_uint64_t x9;
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rt_uint64_t x6;
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rt_uint64_t x7;
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rt_uint64_t x4;
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rt_uint64_t x5;
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rt_uint64_t x2;
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rt_uint64_t x3;
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rt_uint64_t x0;
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rt_uint64_t x1;
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rt_uint128_t fpu[32];
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};
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void rt_hw_show_register(struct rt_hw_exp_stack *regs);
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#define SP_ELx ((unsigned long)0x01)
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#define SP_EL0 ((unsigned long)0x00)
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#define PSTATE_EL1 ((unsigned long)0x04)
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#define PSTATE_EL2 ((unsigned long)0x08)
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#define PSTATE_EL3 ((unsigned long)0x0c)
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rt_ubase_t rt_hw_get_current_el(void);
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void rt_hw_set_elx_env(void);
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void rt_hw_set_current_vbar(rt_ubase_t addr);
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/* ESR:generic */
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#define ARM64_ABORT_WNR(esr) ((esr) & 0x40)
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#define ARM64_ESR_EXTRACT_EC(esr) ((((esr) >> 26) & 0x3fU))
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#define ARM64_ESR_EXTRACT_FSC(esr) ((esr) & 0x3f)
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/* ESR:EC */
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#define ARM64_EC_INST_ABORT_FROM_LO_EXCEPTION (0b100000)
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#define ARM64_EC_INST_ABORT_WITHOUT_A_CHANGE (0b100001)
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#define ARM64_EC_DATA_ABORT_FROM_LO_EXCEPTION (0b100100)
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#define ARM64_EC_DATA_ABORT_WITHOUT_A_CHANGE (0b100101)
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/* ESR:FSC */
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#define ARM64_FSC_TRANSLATION_FAULT_LEVEL_0 (0b000100)
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#define ARM64_FSC_TRANSLATION_FAULT_LEVEL_1 (0b000101)
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#define ARM64_FSC_TRANSLATION_FAULT_LEVEL_2 (0b000110)
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#define ARM64_FSC_TRANSLATION_FAULT_LEVEL_3 (0b000111)
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#define ARM64_FSC_PERMISSION_FAULT_LEVEL_0 (0b001100)
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#define ARM64_FSC_PERMISSION_FAULT_LEVEL_1 (0b001101)
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#define ARM64_FSC_PERMISSION_FAULT_LEVEL_2 (0b001110)
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#define ARM64_FSC_PERMISSION_FAULT_LEVEL_3 (0b001111)
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#define ARM64_FSC_ACCESS_FLAG_FAULT_LEVEL_0 (0b001000)
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#define ARM64_FSC_ACCESS_FLAG_FAULT_LEVEL_1 (0b001001)
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#define ARM64_FSC_ACCESS_FLAG_FAULT_LEVEL_2 (0b001010)
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#define ARM64_FSC_ACCESS_FLAG_FAULT_LEVEL_3 (0b001011)
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#endif /* __ASSEMBLY__ */
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#endif
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