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https://github.com/RT-Thread/rt-thread.git
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6b0671b336
1.RT_TIMER_TICK_PER_SECOND替换为RT_TICK_PER_SECOND 2.nxp lpc、imx、mcx系列bsp修复 3.lpc824支持gcc 4.lpc824、lpc1114 bsp默认使用nano版本 5.nxp scons --dist问题修复 6.rt-spark lvgl latest 编译修复
88 lines
2.4 KiB
C
88 lines
2.4 KiB
C
/*
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* Copyright 2019 NXP
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* All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include "vglite_support.h"
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#include "fsl_clock.h"
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#include "vg_lite.h"
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#include "vg_lite_platform.h"
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#include "display_support.h"
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/*******************************************************************************
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* Definitions
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******************************************************************************/
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#define MAX_CONTIGUOUS_SIZE 0x200000
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/*******************************************************************************
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* Prototypes
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******************************************************************************/
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/*******************************************************************************
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* Variables
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******************************************************************************/
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static uint32_t registerMemBase = 0x41800000;
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static uint32_t gpu_mem_base = 0x0;
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/*
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* In case custom VGLite memory parameters are used, the application needs to
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* allocate and publish the VGLite heap base, its size and the size of the
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* command buffer(s) using the following global variables:
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*/
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extern void *vglite_heap_base;
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extern uint32_t vglite_heap_size;
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#if (CUSTOM_VGLITE_MEMORY_CONFIG == 0)
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/* VGLite driver heap */
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AT_NONCACHEABLE_SECTION_ALIGN(static uint8_t contiguous_mem[MAX_CONTIGUOUS_SIZE], FRAME_BUFFER_ALIGN);
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void *vglite_heap_base = &contiguous_mem;
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uint32_t vglite_heap_size = MAX_CONTIGUOUS_SIZE;
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#endif /* CUSTOM_VGLITE_MEMORY_CONFIG */
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/*******************************************************************************
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* Code
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******************************************************************************/
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void GPU2D_IRQHandler(void)
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{
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vg_lite_IRQHandler();
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}
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static status_t BOARD_InitVGliteClock(void)
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{
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const clock_root_config_t gc355ClockConfig = {
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.clockOff = false,
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.mux = kCLOCK_GC355_ClockRoot_MuxVideoPllOut, /*!< 984MHz */
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.div = 2,
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};
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CLOCK_SetRootClock(kCLOCK_Root_Gc355, &gc355ClockConfig);
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CLOCK_GetRootClockFreq(kCLOCK_Root_Gc355);
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CLOCK_EnableClock(kCLOCK_Gpu2d);
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NVIC_SetPriority(GPU2D_IRQn, 3);
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EnableIRQ(GPU2D_IRQn);
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return kStatus_Success;
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}
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status_t BOARD_PrepareVGLiteController(void)
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{
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status_t status;
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status = BOARD_InitVGliteClock();
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if (kStatus_Success != status)
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{
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return status;
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}
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vg_lite_init_mem(registerMemBase, gpu_mem_base, vglite_heap_base, vglite_heap_size);
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return kStatus_Success;
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}
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