101 lines
2.2 KiB
C
101 lines
2.2 KiB
C
/*
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* Copyright (c) 2006-2018, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2017-09-06 勤为本 first version
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*
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* Copyright (c) 2020, duhuanpeng<548708880@qq.com>
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* legacy driver APIs from loongson 1C BSP.
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*/
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#include <rtthread.h>
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#include "ls2k1000.h"
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struct loongson_pll {
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rt_uint64_t PLL_SYS_0;
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rt_uint64_t PLL_SYS_1;
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rt_uint64_t PLL_DDR_0;
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rt_uint64_t PLL_DDR_1;
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rt_uint64_t PLL_DC_0;
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rt_uint64_t PLL_DC_1;
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rt_uint64_t PLL_PIX0_0;
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rt_uint64_t PLL_PIX0_1;
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rt_uint64_t PLL_PIX1_0;
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rt_uint64_t PLL_PIX1_1;
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rt_uint64_t FREQSCALE;
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};
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/* See the Schematic */
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#define SYS_CLKSEL1 1
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#define SYS_CLKSEL0 0
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/* bit field helpers. */
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#define __M(n) (~(~0<<(n)))
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#define __RBF(number, n) ((number)&__M(n))
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#define __BF(number, n, m) __RBF((number>>m), (n-m+1))
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#define BF(number, n, m) (m<n ? __BF(number, n, m) : __BF(number, m, n))
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int refclk = 100;
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int gmac_clock = 125;
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volatile struct loongson_pll *pll = (void *)PLL_SYS_BASE;
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unsigned long clk_get_pll_rate(void)
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{
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return -RT_ENOSYS;
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}
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unsigned long clk_get_cpu_rate(void)
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{
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unsigned long node_clock;
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int l1_div_ref;
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int l1_div_loopc;
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int l2_div_out_node;
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l1_div_ref = BF(pll->PLL_SYS_0, 26, 31);
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l1_div_loopc = BF(pll->PLL_SYS_0, 32, 41);
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l2_div_out_node = BF(pll->PLL_SYS_1, 5, 0);
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node_clock = refclk / l1_div_ref * l1_div_loopc / l2_div_out_node;
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return node_clock;
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}
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unsigned long clk_get_ddr_rate(void)
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{
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unsigned long ddr_clock;
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int l1_div_ref;
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int l1_div_loopc;
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int l2_div_out_ddr;
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l1_div_ref = BF(pll->PLL_DDR_0, 26, 31);
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l1_div_loopc = BF(pll->PLL_DDR_0, 32, 41);
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l2_div_out_ddr = BF(pll->PLL_DDR_1, 0, 5);
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ddr_clock = refclk / l1_div_ref * l1_div_loopc / l2_div_out_ddr;
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return ddr_clock;
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}
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unsigned long clk_get_apb_rate(void)
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{
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unsigned long apb_clock;
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int apb_freqscale;
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apb_freqscale = BF(pll->FREQSCALE, 22, 20);
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/* gmac clock is fixed 125MHz */
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apb_clock = gmac_clock * (apb_freqscale + 1) / 8;
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return apb_clock;
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}
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unsigned long clk_get_dc_rate(void)
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{
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return -RT_ENOSYS;
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}
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