327 lines
8.0 KiB
C
327 lines
8.0 KiB
C
/*
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* Copyright (c) 2006-2023, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2017-08-08 Yang the first version
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* 2019-07-19 Magicoe The first version for LPC55S6x
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* 2023-02-0 Alex Yang update driver
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*/
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#include "board.h"
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#include <rtdevice.h>
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#include "fsl_sdif.h"
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#ifdef RT_USING_SDIO
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//#define MMCSD_DEBUG
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#ifdef MMCSD_DEBUG
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#define MMCSD_DGB rt_kprintf
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#else
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#define MMCSD_DGB(fmt, ...)
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#endif
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#define SDMMCHOST_RESET_TIMEOUT_VALUE (1000000U)
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struct lpc_mmcsd
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{
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struct rt_mmcsd_host *host;
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SDIF_Type *SDIFx;
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uint32_t sdmmcHostDmaBuffer[0x40];
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};
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static void SDMMCHOST_ErrorRecovery(SDIF_Type *base)
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{
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(void)SDIF_Reset(base, kSDIF_ResetAll, SDMMCHOST_RESET_TIMEOUT_VALUE);
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/* the host controller clock will be disabled by the reset operation, so re-send the clock sync command to enable
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the output clock */
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sdif_command_t clockSync = {
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.flags = kSDIF_WaitPreTransferComplete | kSDIF_CmdUpdateClockRegisterOnly, .index = 0U, .argument = 0U};
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(void)SDIF_SendCommand(base, &clockSync, 0U);
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}
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static void lpc_sdmmc_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req)
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{
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struct lpc_mmcsd *mmcsd;
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struct rt_mmcsd_cmd *cmd;
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struct rt_mmcsd_data *data;
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rt_uint32_t *buf = NULL;
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status_t error;
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mmcsd = (struct lpc_mmcsd *) host->private_data;
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cmd = req->cmd;
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data = cmd->data;
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sdif_dma_config_t dmaConfig;
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dmaConfig.enableFixBurstLen = false;
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dmaConfig.mode = kSDIF_ChainDMAMode;
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dmaConfig.dmaDesBufferStartAddr = mmcsd->sdmmcHostDmaBuffer;
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dmaConfig.dmaDesBufferLen = 0x40;
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dmaConfig.dmaDesSkipLen = 0U;
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sdif_transfer_t fsl_content = {0};
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sdif_command_t fsl_command = {0};
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sdif_data_t fsl_data = {0};
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fsl_content.command = &fsl_command;
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fsl_content.data = &fsl_data;
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// MMCSD_DGB("ARG:0x%X, CODE:0x%X\r\n", cmd->arg, cmd->cmd_code);
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fsl_command.index = cmd->cmd_code;
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fsl_command.argument = cmd->arg;
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if (cmd->cmd_code == STOP_TRANSMISSION)
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fsl_command.type = kCARD_CommandTypeAbort;
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else
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fsl_command.type = kCARD_CommandTypeNormal;
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switch (cmd->flags & RESP_MASK)
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{
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case RESP_NONE:
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fsl_command.responseType = kCARD_ResponseTypeNone;
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break;
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case RESP_R1:
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fsl_command.responseType = kCARD_ResponseTypeR1;
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break;
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case RESP_R1B:
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fsl_command.responseType = kCARD_ResponseTypeR1b;
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break;
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case RESP_R2:
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fsl_command.responseType = kCARD_ResponseTypeR2;
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break;
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case RESP_R3:
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fsl_command.responseType = kCARD_ResponseTypeR3;
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break;
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case RESP_R4:
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fsl_command.responseType = kCARD_ResponseTypeR4;
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break;
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case RESP_R6:
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fsl_command.responseType = kCARD_ResponseTypeR6;
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break;
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case RESP_R7:
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fsl_command.responseType = kCARD_ResponseTypeR7;
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break;
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case RESP_R5:
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fsl_command.responseType = kCARD_ResponseTypeR5;
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break;
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default:
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RT_ASSERT(NULL);
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}
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fsl_command.flags = 0;
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fsl_content.command = &fsl_command;
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if (data)
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{
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if (req->stop != NULL)
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fsl_data.enableAutoCommand12 = true;
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else
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fsl_data.enableAutoCommand12 = false;
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fsl_data.enableIgnoreError = false;
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fsl_data.blockSize = data->blksize;
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fsl_data.blockCount = data->blks;
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if ((cmd->cmd_code == WRITE_BLOCK) || (cmd->cmd_code == WRITE_MULTIPLE_BLOCK))
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{
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if (buf)
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{
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MMCSD_DGB(" write(data->buf to buf) ");
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rt_memcpy(buf, data->buf, fsl_data.blockSize * fsl_data.blockCount);
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fsl_data.txData = (uint32_t const *)buf;
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}
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else
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{
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fsl_data.txData = (uint32_t const *)data->buf;
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}
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fsl_data.rxData = NULL;
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}
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else
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{
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if (buf)
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{
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fsl_data.rxData = (uint32_t *)buf;
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}
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else
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{
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fsl_data.rxData = (uint32_t *)data->buf;
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}
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fsl_data.txData = NULL;
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}
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fsl_content.data = &fsl_data;
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}
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else
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{
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fsl_content.data = NULL;
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}
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error = SDIF_TransferBlocking(mmcsd->SDIFx, &dmaConfig, &fsl_content);
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if (error != kStatus_Success)
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{
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SDMMCHOST_ErrorRecovery(mmcsd->SDIFx);
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MMCSD_DGB(" ***SDIF_TransferBlocking error: %d*** --> \n", error);
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cmd->err = -RT_ERROR;
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}
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if (buf)
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{
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if (fsl_data.rxData)
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{
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MMCSD_DGB("read copy buf to data->buf ");
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rt_memcpy(data->buf, buf, fsl_data.blockSize * fsl_data.blockCount);
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}
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rt_free_align(buf);
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}
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if ((cmd->flags & RESP_MASK) == RESP_R2)
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{
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cmd->resp[3] = fsl_command.response[0];
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cmd->resp[2] = fsl_command.response[1];
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cmd->resp[1] = fsl_command.response[2];
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cmd->resp[0] = fsl_command.response[3];
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// MMCSD_DGB(" resp 0x%08X 0x%08X 0x%08X 0x%08X\n", cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3]);
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}
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else
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{
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cmd->resp[0] = fsl_command.response[0];
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// MMCSD_DGB(" resp 0x%08X\n", cmd->resp[0]);
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}
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mmcsd_req_complete(host);
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}
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static void lpc_sdmmc_set_iocfg(struct rt_mmcsd_host *host, struct rt_mmcsd_io_cfg *io_cfg)
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{
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//rt_kprintf("%s\r\n", __FUNCTION__);
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struct lpc_mmcsd *mmcsd;
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mmcsd = (struct lpc_mmcsd *) host->private_data;
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uint32_t sdxc_clock = io_cfg->clock;
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MMCSD_DGB("sdxc_clock:%d\r\n", sdxc_clock);
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MMCSD_DGB("bus_width:%d\r\n", io_cfg->bus_width);
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if (sdxc_clock != 0U)
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{
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SDIF_SetCardClock(mmcsd->SDIFx, CLOCK_GetSdioClkFreq(), sdxc_clock);
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switch (io_cfg->bus_width)
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{
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case MMCSD_BUS_WIDTH_4:
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SDIF_SetCardBusWidth(mmcsd->SDIFx, kSDIF_Bus4BitWidth);
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break;
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case MMCSD_BUS_WIDTH_8:
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SDIF_SetCardBusWidth(mmcsd->SDIFx, kSDIF_Bus8BitWidth);
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break;
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default:
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SDIF_SetCardBusWidth(mmcsd->SDIFx, kSDIF_Bus1BitWidth);
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break;
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}
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}
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rt_thread_mdelay(20);
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}
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static const struct rt_mmcsd_host_ops lpc_mmcsd_host_ops =
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{
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.request = lpc_sdmmc_request,
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.set_iocfg = lpc_sdmmc_set_iocfg,
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.get_card_status = NULL,
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.enable_sdio_irq = NULL, // Do not use the interrupt mode, use DMA instead
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};
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int rt_hw_sdio_init(void)
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{
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struct rt_mmcsd_host *host = NULL;
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struct lpc_mmcsd *mmcsd = NULL;
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host = mmcsd_alloc_host();
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if (!host)
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{
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return -RT_ERROR;
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}
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mmcsd = rt_malloc(sizeof(struct lpc_mmcsd));
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if (!mmcsd)
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{
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rt_kprintf("alloc mci failed\n");
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goto err;
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}
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rt_memset(mmcsd, 0, sizeof(struct lpc_mmcsd));
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mmcsd->SDIFx = SDIF;
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host->ops = &lpc_mmcsd_host_ops;
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host->freq_min = 375000;
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host->freq_max = 50000000;
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host->valid_ocr = VDD_30_31 | VDD_31_32 | VDD_32_33 | VDD_33_34;
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host->flags = MMCSD_MUTBLKWRITE | MMCSD_BUSWIDTH_4 | MMCSD_SUP_HIGHSPEED | MMCSD_SUP_SDIO_IRQ;
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host->max_seg_size = 65535;
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host->max_dma_segs = 2;
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host->max_blk_size = 512;
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host->max_blk_count = 4096;
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mmcsd->host = host;
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/* Perform necessary initialization */
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CLOCK_AttachClk(kMAIN_CLK_to_SDIO_CLK);
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CLOCK_SetClkDiv(kCLOCK_DivSdioClk, (uint32_t)(SystemCoreClock / FSL_FEATURE_SDIF_MAX_SOURCE_CLOCK + 1U), true);
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MMCSD_DGB("SDIO clock:%dHz\r\n", CLOCK_GetSdioClkFreq());
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sdif_config_t sdif_config = {0};
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sdif_config.responseTimeout = 0xFFU;
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sdif_config.cardDetDebounce_Clock = 0xFFFFFFU;
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sdif_config.dataTimeout = 0xFFFFFFU;
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SDIF_Init(mmcsd->SDIFx, &sdif_config);
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SDIF_EnableCardPower(mmcsd->SDIFx, false);
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SDIF_EnableCardPower(mmcsd->SDIFx, true);
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host->private_data = mmcsd;
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mmcsd_change(host);
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return 0;
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err:
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mmcsd_free_host(host);
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return -RT_ENOMEM;
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}
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INIT_DEVICE_EXPORT(rt_hw_sdio_init);
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#endif /* endif RT_USING_SDIO */
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