441 lines
15 KiB
Plaintext
441 lines
15 KiB
Plaintext
/***************************************************************************//**
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* \file xmc7200_x8384_cm7.ld
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* \version 1.0.0
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*
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* Linker file for the GNU C compiler.
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*
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* The main purpose of the linker script is to describe how the sections in the
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* input files should be mapped into the output file, and to control the memory
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* layout of the output file.
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*
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* \note The entry point location is fixed and starts at 0x10000000. The valid
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* application image should be placed there.
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*
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* \note The linker files included with the PDL template projects must be generic
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* and handle all common use cases. Your project may not use every section
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* defined in the linker files. In that case you may see warnings during the
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* build process. In your project, you can simply comment out or remove the
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* relevant code in the linker file.
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*
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********************************************************************************
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* \copyright
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* Copyright 2021 Cypress Semiconductor Corporation
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*******************************************************************************/
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OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
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GROUP(-lgcc -lc -lnosys )
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SEARCH_DIR(.)
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GROUP(libgcc.a libc.a libm.a libnosys.a)
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ENTRY(Reset_Handler)
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/* The size of the stack section at the end of CM7 SRAM */
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STACK_SIZE = 0x1000;
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RAMVECTORS_ALIGNMENT = 128;
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sram_start_reserve = 0;
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sram_total_size = 0x00100000; /* SRAM0 + SRAM1 */
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sram_private_for_srom = 0x00000800; /* Private SRAM for SROM (e.g. API processing) */
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sram_used_by_boot = 0x0; /* Used during boot by Cypress firmware (content will be overwritten on reset, so it should not be used for loadable sections in case of RAM build configurations) */
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cm0plus_sram_reserve = 0x00004000; /* 16K : cm0 sram size */
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cm7_0_sram_reserve = 0x000FC000; /* 1008K : cm7_0 sram size */
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code_flash_total_size = 0x00830000; /* 8384K: total flash size */
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cm0plus_code_flash_reserve = 0x00080000; /* 512K : cm0 flash size */
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cm7_0_code_flash_reserve = 0x007B0000; /* 7872K: cm7_0 flash size */
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code_flash_base_address = 0x10000000;
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sram_base_address = 0x28000000;
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/* SRAM reservations */
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_base_SRAM_CM7_0 = sram_base_address + cm0plus_sram_reserve;
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_size_SRAM_CM7_0 = cm7_0_sram_reserve;
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/* Code flash reservations */
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_base_CODE_FLASH_CM0P = code_flash_base_address;
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_size_CODE_FLASH_CM0P = cm0plus_code_flash_reserve;
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_base_CODE_FLASH_CM7_0 = code_flash_base_address + cm0plus_code_flash_reserve;
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_size_CODE_FLASH_CM7_0 = cm7_0_code_flash_reserve;
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/* Fixed Addresses */
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_base_WORK_FLASH = 0x14000000;
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_size_WORK_FLASH = 0x00040000; /* 256K Work flash */
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_base_CM7_0_ITCM = 0x00000000;
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_size_CM7_0_ITCM = 0x00004000;
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_base_CM7_0_DTCM = 0x20000000;
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_size_CM7_0_DTCM = 0x00004000;
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/* For the non-dual cm7 device, _CORE_CM7_0_ should be defined and _CORE_CM7_1_ should not be defined */
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_base_SRAM = _base_SRAM_CM7_0;
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_size_SRAM = _size_SRAM_CM7_0;
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_base_CODE_FLASH = _base_CODE_FLASH_CM7_0;
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_size_CODE_FLASH = _size_CODE_FLASH_CM7_0;
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_base_SFLASH_USER_DATA = 0x17000800;
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_size_SFLASH_USER_DATA = 0x00000800;
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_base_SFLASH_NAR = 0x17001A00;
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_size_SFLASH_NAR = 0x00000200;
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_base_SFLASH_PUB_KEY = 0x17006400;
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_size_SFLASH_PUB_KEY = 0x00000C00;
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_base_SFLASH_APP_PROT = 0x17007600;
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_size_SFLASH_APP_PROT = 0x00000200;
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_base_SFLASH_TOC2 = 0x17007C00;
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_size_SFLASH_TOC2 = 0x00000200;
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_base_XIP = 0x60000000;
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_size_XIP = 0x08000000;
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_base_EFUSE = 0x90700000;
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_size_EFUSE = 0x00100000;
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_base_ITCM = _base_CM7_0_ITCM;
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_size_ITCM = _size_CM7_0_ITCM;
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_base_DTCM = _base_CM7_0_DTCM;
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_size_DTCM = _size_CM7_0_DTCM;
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/* Force symbol to be entered in the output file as an undefined symbol. Doing
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* this may, for example, trigger linking of additional modules from standard
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* libraries. You may list several symbols for each EXTERN, and you may use
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* EXTERN multiple times. This command has the same effect as the -u command-line
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* option.
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*/
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EXTERN(Reset_Handler)
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/* The MEMORY section below describes the location and size of blocks of memory in the target.
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* Use this section to specify the memory regions available for allocation.
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*/
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MEMORY
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{
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/* The ram and flash regions control RAM and flash memory allocation for the CM7_0/CM7_1 core. */
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ram (rxw) : ORIGIN = _base_SRAM, LENGTH = _size_SRAM /* SRAM */
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flash_cm0p (rx) : ORIGIN = _base_CODE_FLASH_CM0P, LENGTH = _size_CODE_FLASH_CM0P /* CODE flash CM0+ */
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flash (rx) : ORIGIN = _base_CODE_FLASH, LENGTH = _size_CODE_FLASH /* CODE flash CM7_0/1 */
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/* This is a 256K flash region used for EEPROM emulation. This region can also be used as the general purpose flash.
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* You can assign sections to this memory region for only one of the cores.
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*/
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em_eeprom (rw) : ORIGIN = _base_WORK_FLASH, LENGTH = _size_WORK_FLASH /* WORK flash */
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/* The following regions define device specific memory regions and must not be changed. */
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sflash_user_data (rx) : ORIGIN = _base_SFLASH_USER_DATA, LENGTH = _size_SFLASH_USER_DATA /* Supervisory flash: User data */
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sflash_nar (rx) : ORIGIN = _base_SFLASH_NAR, LENGTH = _size_SFLASH_NAR /* Supervisory flash: Normal Access Restrictions (NAR) */
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sflash_public_key (rx) : ORIGIN = _base_SFLASH_PUB_KEY, LENGTH = _size_SFLASH_PUB_KEY /* Supervisory flash: Public Key */
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sflash_app_prot (rx) : ORIGIN = _base_SFLASH_APP_PROT, LENGTH = _size_SFLASH_APP_PROT
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sflash_toc_2 (rx) : ORIGIN = _base_SFLASH_TOC2, LENGTH = _size_SFLASH_TOC2 /* Supervisory flash: Table of Content # 2 */
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xip (rx) : ORIGIN = _base_XIP, LENGTH = _size_XIP /* XIP: 128 MB */
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efuse (rx) : ORIGIN = _base_EFUSE, LENGTH = _size_EFUSE /* 1MB */
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itcm (rx) : ORIGIN = _base_ITCM, LENGTH = _size_ITCM /* ITCM */
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dtcm (rx) : ORIGIN = _base_DTCM, LENGTH = _base_DTCM /* DTCM */
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}
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/* Library configurations */
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GROUP(libgcc.a libc.a libm.a libnosys.a)
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SECTIONS
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{
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/* Cortex-M0+ application flash image area. Comment this section if you don't want to include CM0+ image */
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.cy_cm0p_image ORIGIN(flash_cm0p):
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{
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. = ALIGN(4);
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__cy_m0p_code_start = . ;
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KEEP(*(.cy_m0p_image))
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__cy_m0p_code_end = . ;
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} > flash_cm0p
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/* Check if .cy_m0p_image size exceeds cm0plus_code_flash_reserve */
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ASSERT(__cy_m0p_code_end < ORIGIN(flash), "CM0+ flash image overflows with CM7, increase CM7 base address ")
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/* Cortex-M7 application flash area */
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.text ORIGIN(flash) :
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{
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/* Cortex-M7 flash vector table */
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. = ALIGN(4);
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__Vectors = . ;
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KEEP(*(.vectors))
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. = ALIGN(4);
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__Vectors_End = .;
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__Vectors_Size = __Vectors_End - __Vectors;
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__end__ = .;
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. = ALIGN(4);
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*(.text*)
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KEEP(*(.init))
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KEEP(*(.fini))
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/* .ctors */
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*crtbegin.o(.ctors)
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*crtbegin?.o(.ctors)
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*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
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*(SORT(.ctors.*))
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*(.ctors)
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/* .dtors */
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*crtbegin.o(.dtors)
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*crtbegin?.o(.dtors)
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*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
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*(SORT(.dtors.*))
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*(.dtors)
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/* Read-only code (constants). */
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*(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
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KEEP(*(.eh_frame*))
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} > flash
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.ARM.extab :
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{
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*(.ARM.extab* .gnu.linkonce.armextab.*)
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} > flash
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__exidx_start = .;
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.ARM.exidx :
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{
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*(.ARM.exidx* .gnu.linkonce.armexidx.*)
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} > flash
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__exidx_end = .;
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.copy.table :
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{
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. = ALIGN(4);
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__copy_table_start__ = .;
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/* Copy data section to RAM */
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LONG (__etext) /* From */
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LONG (__data_start__) /* To */
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LONG ((__data_end__ - __data_start__)/4) /* Size */
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/* Copy code to ITCM */
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LONG (__zero_table_end__) /* From */
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LONG (__itcm_start__) /* To */
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LONG ((__itcm_end__ - __itcm_start__)/4) /* Size */
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/* Copy data to DTCM */
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LONG (__itcm_flash_end__) /* From */
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LONG (__dtcm_start__) /* To */
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LONG ((__dtcm_end__ - __dtcm_start__)/4) /* Size */
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__copy_table_end__ = .;
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} > flash
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.zero.table :
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{
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. = ALIGN(4);
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__zero_table_start__ = .;
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LONG (__bss_start__)
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LONG ((__bss_end__ - __bss_start__)/4)
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__zero_table_end__ = .;
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} > flash
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/* itcm */
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.cy_itcm ORIGIN(itcm):
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{
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__itcm_start__ = .;
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KEEP(*(.cy_itcm))
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__itcm_end__ = .;
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} > itcm AT>flash
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__itcm_flash_end__ = __zero_table_end__ + (__itcm_end__ - __itcm_start__);
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/* dtcm */
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.cy_dtcm ORIGIN(dtcm):
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{
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__dtcm_start__ = .;
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KEEP(*(.cy_dtcm))
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__dtcm_end__ = .;
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} > dtcm AT>flash
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__etext = __itcm_flash_end__ + (__dtcm_end__ - __dtcm_start__) ;
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.ramVectors (NOLOAD) :
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{
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. = ALIGN(RAMVECTORS_ALIGNMENT);
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__ram_vectors_start__ = .;
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KEEP(*(.ram_vectors))
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__ram_vectors_end__ = .;
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} > ram
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.data __ram_vectors_end__ :
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{
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. = ALIGN(4);
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__data_start__ = .;
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*(vtable)
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*(.data*)
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. = ALIGN(4);
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/* preinit data */
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PROVIDE_HIDDEN (__preinit_array_start = .);
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KEEP(*(.preinit_array))
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PROVIDE_HIDDEN (__preinit_array_end = .);
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. = ALIGN(4);
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/* init data */
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PROVIDE_HIDDEN (__init_array_start = .);
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KEEP(*(SORT(.init_array.*)))
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KEEP(*(.init_array))
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PROVIDE_HIDDEN (__init_array_end = .);
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. = ALIGN(4);
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/* finit data */
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PROVIDE_HIDDEN (__fini_array_start = .);
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KEEP(*(SORT(.fini_array.*)))
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KEEP(*(.fini_array))
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PROVIDE_HIDDEN (__fini_array_end = .);
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KEEP(*(.jcr*))
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. = ALIGN(4);
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KEEP(*(.cy_ramfunc*))
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. = ALIGN(32);
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KEEP(*(cy_sharedmem*))
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. = ALIGN(4);
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__data_end__ = .;
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} > ram AT>flash
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/* Place variables in the section that should not be initialized during the
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* device startup.
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*/
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.noinit (NOLOAD) : ALIGN(8)
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{
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KEEP(*(.noinit))
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} > ram
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/* The uninitialized global or static variables are placed in this section.
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*
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* The NOLOAD attribute tells linker that .bss section does not consume
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* any space in the image. The NOLOAD attribute changes the .bss type to
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* NOBITS, and that makes linker to A) not allocate section in memory, and
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* A) put information to clear the section with all zeros during application
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* loading.
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*
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* Without the NOLOAD attribute, the .bss section might get PROGBITS type.
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* This makes linker to A) allocate zeroed section in memory, and B) copy
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* this section to RAM during application loading.
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*/
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.bss (NOLOAD):
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{
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. = ALIGN(4);
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__bss_start__ = .;
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*(.bss*)
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*(COMMON)
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. = ALIGN(4);
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__bss_end__ = .;
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} > ram
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.heap (NOLOAD):
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{
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__HeapBase = .;
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__end__ = .;
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end = __end__;
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KEEP(*(.heap*))
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. = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE;
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__HeapLimit = .;
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} > ram
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/* .stack_dummy section doesn't contains any symbols. It is only
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* used for linker to calculate size of stack sections, and assign
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* values to stack symbols later */
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.stack_dummy (NOLOAD):
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{
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KEEP(*(.stack*))
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} > ram
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/* Set stack top to end of RAM, and stack limit move down by
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* size of stack_dummy section */
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__StackTop = ORIGIN(ram) + LENGTH(ram);
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__StackLimit = __StackTop - STACK_SIZE;
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PROVIDE(__stack = __StackTop);
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/* Check if data + heap + stack exceeds RAM limit */
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ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
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/* Emulated EEPROM Flash area */
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.cy_em_eeprom :
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{
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KEEP(*(.cy_em_eeprom))
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} > em_eeprom
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/* Supervisory Flash: User data */
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.cy_sflash_user_data :
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{
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KEEP(*(.cy_sflash_user_data))
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} > sflash_user_data
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/* Supervisory Flash: Normal Access Restrictions (NAR) */
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.cy_sflash_nar :
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{
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KEEP(*(.cy_sflash_nar))
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} > sflash_nar
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/* Supervisory Flash: Public Key */
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.cy_sflash_public_key :
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{
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KEEP(*(.cy_sflash_public_key))
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} > sflash_public_key
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/* Supervisory Flash: Table of Content # 2 */
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.cy_toc_part2 :
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{
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KEEP(*(.cy_toc_part2))
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} > sflash_toc_2
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/* Places the code in the Execute in Place (XIP) section. See the smif driver
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* documentation for details.
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*/
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cy_xip :
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{
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__cy_xip_start = .;
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KEEP(*(.cy_xip))
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__cy_xip_end = .;
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} > xip
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/* eFuse */
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.cy_efuse :
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{
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KEEP(*(.cy_efuse))
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} > efuse
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}
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/*============================================================
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* Symbols for use by application
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*============================================================
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*/
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__ecc_init_sram_start_address = ORIGIN(ram);
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__ecc_init_sram_end_address = ORIGIN(ram) + LENGTH(ram);
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/* EOF */
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