648 lines
29 KiB
C
648 lines
29 KiB
C
/*****************************************************************************
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* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
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*
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* This software component is licensed by HDSC under BSD 3-Clause license
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* (the "License"); You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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*/
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/******************************************************************************/
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/** \file hc32f460_clk.h
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**
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** A detailed description is available at
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** @link CmuGroup Clock description @endlink
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**
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** - 2018-10-13 CDT First version for Device Driver Library of CMU.
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**
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******************************************************************************/
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#ifndef __HC32F460_CLK_H__
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#define __HC32F460_CLK_H__
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/*******************************************************************************
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* Include files
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******************************************************************************/
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#include "hc32_common.h"
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#include "ddl_config.h"
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#if (DDL_CLK_ENABLE == DDL_ON)
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/* C binding of definitions if building with C++ compiler */
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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/**
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*******************************************************************************
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** \defgroup CmuGroup Clock Manage Unit(CMU)
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**
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******************************************************************************/
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//@{
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/*******************************************************************************
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* Global type definitions ('typedef')
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******************************************************************************/
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/**
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*******************************************************************************
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** \brief The system clock source.
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**
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******************************************************************************/
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typedef enum en_clk_sys_source
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{
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ClkSysSrcHRC = 0u, ///< The system clock source is HRC.
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ClkSysSrcMRC = 1u, ///< The system clock source is MRC.
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ClkSysSrcLRC = 2u, ///< The system clock source is LRC.
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ClkSysSrcXTAL = 3u, ///< The system clock source is XTAL.
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ClkSysSrcXTAL32 = 4u, ///< The system clock source is XTAL32.
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CLKSysSrcMPLL = 5u, ///< The system clock source is MPLL.
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}en_clk_sys_source_t;
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/**
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*******************************************************************************
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** \brief The pll clock source.
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**
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******************************************************************************/
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typedef enum en_clk_pll_source
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{
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ClkPllSrcXTAL = 0u, ///< The pll clock source is XTAL.
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ClkPllSrcHRC = 1u, ///< The pll clock source is HRC.
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}en_clk_pll_source_t;
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/**
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*******************************************************************************
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** \brief The usb clock source.
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**
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******************************************************************************/
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typedef enum en_clk_usb_source
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{
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ClkUsbSrcSysDiv2 = 2u, ///< The usb clock source is 1/2 system clock.
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ClkUsbSrcSysDiv3 = 3u, ///< The usb clock source is 1/3 system clock.
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ClkUsbSrcSysDiv4 = 4u, ///< The usb clock source is 1/4 system clock.
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ClkUsbSrcMpllp = 8u, ///< The usb clock source is MPLLP.
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ClkUsbSrcMpllq = 9u, ///< The usb clock source is MPLLQ.
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ClkUsbSrcMpllr = 10u, ///< The usb clock source is MPLLR.
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ClkUsbSrcUpllp = 11u, ///< The usb clock source is UPLLP.
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ClkUsbSrcUpllq = 12u, ///< The usb clock source is UPLLQ.
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ClkUsbSrcUpllr = 13u, ///< The usb clock source is UPLLR.
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}en_clk_usb_source_t;
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/**
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*******************************************************************************
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** \brief The peripheral(adc/trng/I2S) clock source.
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**
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******************************************************************************/
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typedef enum en_clk_peri_source
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{
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ClkPeriSrcPclk = 0u, ///< The peripheral(adc/trng/I2S) clock source is division from system clock.
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ClkPeriSrcMpllp = 8u, ///< The peripheral(adc/trng/I2S) clock source is MPLLP.
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ClkPeriSrcMpllq = 9u, ///< The peripheral(adc/trng/I2S) clock source is MPLLQ.
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ClkPeriSrcMpllr = 10u, ///< The peripheral(adc/trng/I2S) clock source is MPLLR.
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ClkPeriSrcUpllp = 11u, ///< The peripheral(adc/trng/I2S) clock source is UPLLP.
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ClkPeriSrcUpllq = 12u, ///< The peripheral(adc/trng/I2S) clock source is UPLLQ.
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ClkPeriSrcUpllr = 13u, ///< The peripheral(adc/trng/I2S) clock source is UPLLR.
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}en_clk_peri_source_t;
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/**
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*******************************************************************************
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** \brief The clock output source.
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**
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******************************************************************************/
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typedef enum en_clk_output_source
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{
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ClkOutputSrcHrc = 0u, ///< The clock output source is HRC
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ClkOutputSrcMrc = 1u, ///< The clock output source is MRC.
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ClkOutputSrcLrc = 2u, ///< The clock output source is LRC.
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ClkOutputSrcXtal = 3u, ///< The clock output source is XTAL.
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ClkOutputSrcXtal32 = 4u, ///< The clock output source is XTAL32
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ClkOutputSrcMpllp = 6u, ///< The clock output source is MPLLP.
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ClkOutputSrcUpllp = 7u, ///< The clock output source is UPLLP.
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ClkOutputSrcMpllq = 8u, ///< The clock output source is MPLLQ.
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ClkOutputSrcUpllq = 9u, ///< The clock output source is UPLLQ.
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ClkOutputSrcSysclk = 11u, ///< The clock output source is system clock.
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}en_clk_output_source_t;
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/**
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*******************************************************************************
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** \brief The clock frequency source for measure or reference.
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**
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******************************************************************************/
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typedef enum en_clk_fcm_source
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{
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ClkFcmSrcXtal = 0u, ///< The clock frequency measure or reference source is XTAL
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ClkFcmSrcXtal32 = 1u, ///< The clock frequency measure or reference source is XTAL32.
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ClkFcmSrcHrc = 2u, ///< The clock frequency measure or reference source is HRC.
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ClkFcmSrcLrc = 3u, ///< The clock frequency measure or reference source is LRC.
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ClkFcmSrcSwdtrc = 4u, ///< The clock frequency measure or reference source is SWDTRC
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ClkFcmSrcPclk1 = 5u, ///< The clock frequency measure or reference source is PCLK1.
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ClkFcmSrcUpllp = 6u, ///< The clock frequency measure or reference source is UPLLP.
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ClkFcmSrcMrc = 7u, ///< The clock frequency measure or reference source is MRC.
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ClkFcmSrcMpllp = 8u, ///< The clock frequency measure or reference source is MPLLP.
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ClkFcmSrcRtcLrc = 9u, ///< The clock frequency measure or reference source is RTCLRC.
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}en_clk_fcm_intref_source_t,en_clk_fcm_measure_source_t;
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/**
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*******************************************************************************
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** \brief The clock flag status.
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**
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******************************************************************************/
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typedef enum en_clk_flag
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{
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ClkFlagHRCRdy = 0u, ///< The clock flag is HRC ready.
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ClkFlagXTALRdy = 1u, ///< The clock flag is XTAL ready.
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ClkFlagMPLLRdy = 2u, ///< The clock flag is MPLL ready.
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ClkFlagUPLLRdy = 3u, ///< The clock flag is UPLL ready.
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ClkFlagXTALStoppage = 4u, ///< The clock flag is XTAL stoppage.
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}en_clk_flag_t;
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/**
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*******************************************************************************
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** \brief The clock frequency measure flag status.
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**
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******************************************************************************/
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typedef enum en_clk_fcm_flag
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{
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ClkFcmFlagErrf = 0u, ///< The clock frequency flag is frequency abnormal.
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ClkFcmFlagMendf = 1u, ///< The clock frequency flag is end of measurement.
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ClkFcmFlagOvf = 2u, ///< The clock frequency flag is counter overflow.
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}en_clk_fcm_flag_t;
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/**
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*******************************************************************************
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** \brief The source of xtal.
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**
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******************************************************************************/
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typedef enum en_clk_xtal_mode
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{
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ClkXtalModeOsc = 0u, ///< Use external high speed osc as source.
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ClkXtalModeExtClk = 1u, ///< Use external clk as source.
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}en_clk_xtal_mode_t;
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/**
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*******************************************************************************
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** \brief The drive capability of xtal.
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**
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******************************************************************************/
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typedef enum en_clk_xtal_drv
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{
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ClkXtalHighDrv = 0u, ///< High drive capability.20MHz~24MHz.
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ClkXtalMidDrv = 1u, ///< Middle drive capability.16MHz~20MHz.
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ClkXtalLowDrv = 2u, ///< Low drive capability.8MHz~16MHz.
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ClkXtalTinyDrv = 3u, ///< Tiny drive capability.8MHz.
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}en_clk_xtal_drv_t;
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/**
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*******************************************************************************
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** \brief The stable time of XTAL.
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**
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** \note It depends on SUPDRV bit.
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******************************************************************************/
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typedef enum en_clk_xtal_stb_cycle
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{
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ClkXtalStbCycle35 = 1u, ///< stable time is 35(36) cycle.
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ClkXtalStbCycle67 = 2u, ///< stable time is 67(68) cycle.
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ClkXtalStbCycle131 = 3u, ///< stable time is 131(132) cycle.
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ClkXtalStbCycle259 = 4u, ///< stable time is 259(260) cycle.
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ClkXtalStbCycle547 = 5u, ///< stable time is 547(548) cycle.
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ClkXtalStbCycle1059 = 6u, ///< stable time is 1059(1060) cycle.
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ClkXtalStbCycle2147 = 7u, ///< stable time is 2147(2148) cycle.
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ClkXtalStbCycle4291 = 8u, ///< stable time is 4291(4292) cycle.
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ClkXtalStbCycle8163 = 9u, ///< stable time is 8163(8164) cycle.
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}en_clk_xtal_stb_cycle_t;
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/**
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*******************************************************************************
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** \brief The handle of xtal stoppage.
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**
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******************************************************************************/
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typedef enum en_clk_xtal_stp_mode
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{
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ClkXtalStpModeInt = 0u, ///< The handle of stoppage is interrupt.
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ClkXtalStpModeReset = 1u, ///< The handle of stoppage is reset.
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}en_clk_xtal_stp_mode_t;
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/**
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*******************************************************************************
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** \brief The drive capability of xtal32.
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**
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******************************************************************************/
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typedef enum en_clk_xtal32_drv
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{
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ClkXtal32MidDrv = 0u, ///< Middle drive capability.32.768KHz.
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ClkXtal32HighDrv = 1u, ///< High drive capability.32.768KHz.
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}en_clk_xtal32_drv_t;
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/**
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*******************************************************************************
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** \brief The filter mode of xtal32.
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**
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******************************************************************************/
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typedef enum en_clk_xtal32_filter_mode
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{
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ClkXtal32FilterModeFull = 0u, ///< Valid in run,stop,power down mode.
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ClkXtal32FilterModePart = 2u, ///< Valid in run mode.
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ClkXtal32FilterModeNone = 3u, ///< Invalid in run,stop,power down mode.
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}en_clk_xtal32_filter_mode_t;
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/**
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*******************************************************************************
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** \brief The division factor of system clock.
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**
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******************************************************************************/
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typedef enum en_clk_sysclk_div_factor
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{
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ClkSysclkDiv1 = 0u, ///< 1 division.
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ClkSysclkDiv2 = 1u, ///< 2 division.
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ClkSysclkDiv4 = 2u, ///< 4 division.
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ClkSysclkDiv8 = 3u, ///< 8 division.
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ClkSysclkDiv16 = 4u, ///< 16 division.
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ClkSysclkDiv32 = 5u, ///< 32 division.
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ClkSysclkDiv64 = 6u, ///< 64 division.
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}en_clk_sysclk_div_factor_t;
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/**
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*******************************************************************************
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** \brief The division factor of system clock.It will be used for debug clock.
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**
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******************************************************************************/
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typedef enum en_clk_tpiuclk_div_factor
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{
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ClkTpiuclkDiv1 = 0u, ///< 1 division.
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ClkTpiuclkDiv2 = 1u, ///< 2 division.
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ClkTpiuclkDiv4 = 2u, ///< 4 division.
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}en_clk_tpiuclk_div_factor_t;
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/**
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*******************************************************************************
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** \brief The division factor of clock output.
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**
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******************************************************************************/
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typedef enum en_clk_output_div_factor
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{
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ClkOutputDiv1 = 0u, ///< 1 division.
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ClkOutputDiv2 = 1u, ///< 2 division.
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ClkOutputDiv4 = 2u, ///< 4 division.
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ClkOutputDiv8 = 3u, ///< 8 division.
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ClkOutputDiv16 = 4u, ///< 16 division.
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ClkOutputDiv32 = 5u, ///< 32 division.
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ClkOutputDiv64 = 6u, ///< 64 division.
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ClkOutputDiv128 = 7u, ///< 128 division.
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}en_clk_output_div_factor_t;
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/**
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*******************************************************************************
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** \brief The division factor of fcm measure source.
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**
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******************************************************************************/
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typedef enum en_clk_fcm_measure_div_factor
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{
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ClkFcmMeaDiv1 = 0u, ///< 1 division.
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ClkFcmMeaDiv4 = 1u, ///< 4 division.
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ClkFcmMeaDiv8 = 2u, ///< 8 division.
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ClkFcmMeaDiv32 = 3u, ///< 32 division.
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}en_clk_fcm_measure_div_factor_t;
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/**
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*******************************************************************************
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** \brief The division factor of fcm reference source.
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**
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******************************************************************************/
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typedef enum en_clk_fcm_intref_div_factor
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{
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ClkFcmIntrefDiv32 = 0u, ///< 32 division.
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ClkFcmIntrefDiv128 = 1u, ///< 128 division.
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ClkFcmIntrefDiv1024 = 2u, ///< 1024 division.
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ClkFcmIntrefDiv8192 = 3u, ///< 8192 division.
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}en_clk_fcm_intref_div_factor_t;
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/**
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*******************************************************************************
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** \brief The edge of the fcm reference source.
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**
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******************************************************************************/
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typedef enum en_clk_fcm_edge
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{
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ClkFcmEdgeRising = 0u, ///< Rising edge.
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ClkFcmEdgeFalling = 1u, ///< Falling edge.
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ClkFcmEdgeBoth = 2u, ///< Both edge.
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}en_clk_fcm_edge_t;
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/**
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*******************************************************************************
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** \brief The filter clock of the fcm reference source.
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**
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******************************************************************************/
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typedef enum en_clk_fcm_filter_clk
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{
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ClkFcmFilterClkNone = 0u, ///< None filter.
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ClkFcmFilterClkFcmSrc = 1u, ///< Use fcm measurement source as filter clock.
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ClkFcmFilterClkFcmSrcDiv4 = 2u, ///< Use 1/4 fcm measurement source as filter clock.
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ClkFcmFilterClkFcmSrcDiv16 = 3u, ///< Use 1/16 fcm measurement source as filter clock.
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}en_clk_fcm_filter_clk_t;
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/**
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*******************************************************************************
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** \brief The fcm reference source.
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**
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******************************************************************************/
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typedef enum en_clk_fcm_refer
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{
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ClkFcmExtRef = 0u, ///< Use external reference.
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ClkFcmInterRef = 1u, ///< Use internal reference.
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}en_clk_fcm_refer_t;
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/**
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*******************************************************************************
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** \brief The handle of fcm abnormal.
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**
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******************************************************************************/
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typedef enum en_clk_fcm_abnormal_handle
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{
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ClkFcmHandleInterrupt = 0u, ///< The handle of fcm abnormal is interrupt.
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ClkFcmHandleReset = 1u, ///< The handle of fcm abnormal is reset.
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}en_clk_fcm_abnormal_handle_t;
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/**
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*******************************************************************************
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** \brief The channel of clock output.
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**
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******************************************************************************/
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typedef enum en_clk_output_ch
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{
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ClkOutputCh1 = 1u, ///< The output of clk is MCO_1.
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ClkOutputCh2 = 2u, ///< The output of clk is MCO_2.
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}en_clk_output_ch_t;
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/**
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*******************************************************************************
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** \brief Configuration structure of XTAL.
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**
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** \note Configures the XTAL if needed.
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**
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******************************************************************************/
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typedef struct stc_clk_xtal_cfg
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{
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en_functional_state_t enFastStartup; ///< Enable fast start up or not.
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en_clk_xtal_mode_t enMode; ///< Select xtal mode.
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en_clk_xtal_drv_t enDrv; ///< Select xtal drive capability.
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}stc_clk_xtal_cfg_t;
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/**
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*******************************************************************************
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** \brief Configuration structure of XTAL stoppage.
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**
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** \note Configures the XTAL stoppage if needed.
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**
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******************************************************************************/
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typedef struct stc_clk_xtal_stp_cfg
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{
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en_functional_state_t enDetect; ///< Enable detect stoppage or not.
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en_clk_xtal_stp_mode_t enMode; ///< Select the handle of xtal stoppage.
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en_functional_state_t enModeReset; ///< Enable reset for handle the xtal stoppage.
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en_functional_state_t enModeInt; ///< Enable interrupt for handle the xtal stoppage.
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}stc_clk_xtal_stp_cfg_t;
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/**
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*******************************************************************************
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** \brief Configuration structure of XTAL32.
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**
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** \note Configures the XTAL32 if needed.
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**
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******************************************************************************/
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typedef struct stc_clk_xtal32_cfg
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{
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en_clk_xtal32_drv_t enDrv; ///< Select xtal32 drive capability.
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en_clk_xtal32_filter_mode_t enFilterMode; ///< The filter mode of xtal32.
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}stc_clk_xtal32_cfg_t;
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/**
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*******************************************************************************
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** \brief Configuration structure of PLL.
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**
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** \note Configures the PLL if needed.
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**
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******************************************************************************/
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typedef struct stc_clk_pll_cfg
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{
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uint32_t PllpDiv; ///< Pllp clk, division factor of VCO out.
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uint32_t PllqDiv; ///< Pllq clk, division factor of VCO out.
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uint32_t PllrDiv; ///< Pllr clk, division factor of VCO out.
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uint32_t plln; ///< Multiplication factor of vco out, ensure between 240M~480M
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uint32_t pllmDiv; ///< Division factor of VCO in, ensure between 1M~12M.
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}stc_clk_mpll_cfg_t, stc_clk_upll_cfg_t;
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/**
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*******************************************************************************
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** \brief Configuration structure of system clock.
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**
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** \note Configures the system clock if needed.
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**
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******************************************************************************/
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typedef struct stc_clk_sysclk_cfg
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{
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en_clk_sysclk_div_factor_t enHclkDiv; ///< Division for hclk.
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en_clk_sysclk_div_factor_t enExclkDiv; ///< Division for exclk.
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en_clk_sysclk_div_factor_t enPclk0Div; ///< Division for pclk0.
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en_clk_sysclk_div_factor_t enPclk1Div; ///< Division for pclk1.
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en_clk_sysclk_div_factor_t enPclk2Div; ///< Division for pclk2.
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en_clk_sysclk_div_factor_t enPclk3Div; ///< Division for pclk3.
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en_clk_sysclk_div_factor_t enPclk4Div; ///< Division for pclk4.
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}stc_clk_sysclk_cfg_t;
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/**
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*******************************************************************************
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** \brief Configuration structure of clock output.
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**
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** \note Configures the clock output if needed.
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**
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******************************************************************************/
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typedef struct stc_clk_output_cfg
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{
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en_clk_output_source_t enOutputSrc; ///< The clock output source.
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en_clk_output_div_factor_t enOutputDiv; ///< The division factor of clock output source.
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}stc_clk_output_cfg_t;
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|
|
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/**
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|
*******************************************************************************
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|
** \brief Configuration structure of fcm window.
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|
**
|
|
** \note Configures the fcm window if needed.
|
|
**
|
|
******************************************************************************/
|
|
typedef struct stc_clk_fcm_window_cfg
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|
{
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uint16_t windowLower; ///< The lower value of the window.
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|
uint16_t windowUpper; ///< The upper value of the window.
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}stc_clk_fcm_window_cfg_t;
|
|
|
|
/**
|
|
*******************************************************************************
|
|
** \brief Configuration structure of fcm measurement.
|
|
**
|
|
** \note Configures the fcm measurement if needed.
|
|
**
|
|
******************************************************************************/
|
|
typedef struct stc_clk_fcm_measure_cfg
|
|
{
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|
en_clk_fcm_measure_source_t enSrc; ///< The measurement source.
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en_clk_fcm_measure_div_factor_t enSrcDiv; ///< The division factor of measurement source.
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}stc_clk_fcm_measure_cfg_t;
|
|
|
|
/**
|
|
*******************************************************************************
|
|
** \brief Configuration structure of fcm reference.
|
|
**
|
|
** \note Configures the fcm reference if needed.
|
|
**
|
|
******************************************************************************/
|
|
typedef struct stc_clk_fcm_reference_cfg
|
|
{
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en_functional_state_t enExtRef; ///< Enable external reference or not.
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en_clk_fcm_edge_t enEdge; ///< The edge of internal reference.
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en_clk_fcm_filter_clk_t enFilterClk; ///< The filter clock of internal reference.
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|
en_clk_fcm_refer_t enRefSel; ///< Select reference.
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|
en_clk_fcm_intref_source_t enIntRefSrc; ///< Select internal reference.
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|
en_clk_fcm_intref_div_factor_t enIntRefDiv; ///< The division factor of internal reference.
|
|
}stc_clk_fcm_reference_cfg_t;
|
|
|
|
/**
|
|
*******************************************************************************
|
|
** \brief Configuration structure of fcm interrupt.
|
|
**
|
|
** \note Configures the fcm interrupt if needed.
|
|
**
|
|
******************************************************************************/
|
|
typedef struct stc_clk_fcm_interrupt_cfg
|
|
{
|
|
en_clk_fcm_abnormal_handle_t enHandleSel; ///< Use interrupt or reset.
|
|
en_functional_state_t enHandleReset; ///< Enable reset or not.
|
|
en_functional_state_t enHandleInterrupt; ///< Enable interrupt or not.
|
|
en_functional_state_t enOvfInterrupt; ///< Enable overflow interrupt or not.
|
|
en_functional_state_t enEndInterrupt; ///< Enable measurement end interrupt or not.
|
|
}stc_clk_fcm_interrupt_cfg_t;
|
|
|
|
/**
|
|
*******************************************************************************
|
|
** \brief Configuration structure of fcm.
|
|
**
|
|
** \note Configures the fcm if needed.
|
|
**
|
|
******************************************************************************/
|
|
typedef struct stc_clk_fcm_cfg
|
|
{
|
|
stc_clk_fcm_window_cfg_t *pstcFcmWindowCfg; ///< Window configuration struct.
|
|
stc_clk_fcm_measure_cfg_t *pstcFcmMeaCfg; ///< Measurement configuration struct.
|
|
stc_clk_fcm_reference_cfg_t *pstcFcmRefCfg; ///< Reference configuration struct.
|
|
stc_clk_fcm_interrupt_cfg_t *pstcFcmIntCfg; ///< Interrupt configuration struct.
|
|
}stc_clk_fcm_cfg_t;
|
|
|
|
/**
|
|
*******************************************************************************
|
|
** \brief Clock frequency structure.
|
|
**
|
|
******************************************************************************/
|
|
typedef struct stc_clk_freq
|
|
{
|
|
uint32_t sysclkFreq; ///< System clock frequency.
|
|
uint32_t hclkFreq; ///< Hclk frequency.
|
|
uint32_t exckFreq; ///< Exclk frequency.
|
|
uint32_t pclk0Freq; ///< Pclk0 frequency.
|
|
uint32_t pclk1Freq; ///< Pclk1 frequency.
|
|
uint32_t pclk2Freq; ///< Pclk2 frequency.
|
|
uint32_t pclk3Freq; ///< Pclk3 frequency.
|
|
uint32_t pclk4Freq; ///< Pclk4 frequency.
|
|
}stc_clk_freq_t;
|
|
|
|
/**
|
|
*******************************************************************************
|
|
** \brief PLL Clock frequency structure.
|
|
**
|
|
******************************************************************************/
|
|
typedef struct stc_pll_clk_freq
|
|
{
|
|
uint32_t mpllp; ///< mpllp clock frequency.
|
|
uint32_t mpllq; ///< mpllq clock frequency.
|
|
uint32_t mpllr; ///< mpllr clock frequency.
|
|
uint32_t upllp; ///< upllp clock frequency.
|
|
uint32_t upllq; ///< upllq clock frequency.
|
|
uint32_t upllr; ///< upllr clock frequency.
|
|
}stc_pll_clk_freq_t;
|
|
|
|
/*******************************************************************************
|
|
* Global pre-processor symbols/macros ('#define')
|
|
******************************************************************************/
|
|
|
|
|
|
/*******************************************************************************
|
|
* Global variable definitions ('extern')
|
|
******************************************************************************/
|
|
|
|
/*******************************************************************************
|
|
* Global function prototypes (definition in C source)
|
|
******************************************************************************/
|
|
void CLK_XtalConfig(const stc_clk_xtal_cfg_t *pstcXtalCfg);
|
|
void CLK_XtalStbConfig(const en_clk_xtal_stb_cycle_t enXtalStb);
|
|
void CLK_XtalStpConfig(const stc_clk_xtal_stp_cfg_t *pstcXtalStpCfg);
|
|
en_result_t CLK_XtalCmd(en_functional_state_t enNewState);
|
|
|
|
void CLK_Xtal32Config(const stc_clk_xtal32_cfg_t *pstcXtal32Cfg);
|
|
en_result_t CLK_Xtal32Cmd(en_functional_state_t enNewState);
|
|
|
|
void CLK_HrcTrim(int8_t trimValue);
|
|
en_result_t CLK_HrcCmd(en_functional_state_t enNewState);
|
|
|
|
void CLK_MrcTrim(int8_t trimValue);
|
|
en_result_t CLK_MrcCmd(en_functional_state_t enNewState);
|
|
|
|
void CLK_LrcTrim(int8_t trimValue);
|
|
en_result_t CLK_LrcCmd(en_functional_state_t enNewState);
|
|
|
|
void CLK_SetPllSource(en_clk_pll_source_t enPllSrc);
|
|
void CLK_MpllConfig(const stc_clk_mpll_cfg_t *pstcMpllCfg);
|
|
en_result_t CLK_MpllCmd(en_functional_state_t enNewState);
|
|
|
|
void CLK_UpllConfig(const stc_clk_upll_cfg_t *pstcUpllCfg);
|
|
en_result_t CLK_UpllCmd(en_functional_state_t enNewState);
|
|
|
|
void CLK_SetSysClkSource(en_clk_sys_source_t enTargetSysSrc);
|
|
en_clk_sys_source_t CLK_GetSysClkSource(void);
|
|
|
|
void CLK_SysClkConfig(const stc_clk_sysclk_cfg_t *pstcSysclkCfg);
|
|
void CLK_GetClockFreq(stc_clk_freq_t *pstcClkFreq);
|
|
void CLK_GetPllClockFreq(stc_pll_clk_freq_t *pstcPllClkFreq);
|
|
|
|
void CLK_SetUsbClkSource(en_clk_usb_source_t enTargetUsbSrc);
|
|
void CLK_SetPeriClkSource(en_clk_peri_source_t enTargetPeriSrc);
|
|
void CLK_SetI2sClkSource(const M4_I2S_TypeDef* pstcI2sReg, en_clk_peri_source_t enTargetPeriSrc);
|
|
en_clk_peri_source_t CLK_GetI2sClkSource(const M4_I2S_TypeDef* pstcI2sReg);
|
|
|
|
void CLK_TpiuClkConfig(const en_clk_tpiuclk_div_factor_t enTpiuDiv);
|
|
void CLK_TpiuClkCmd(en_functional_state_t enNewState);
|
|
|
|
void CLK_OutputClkConfig(en_clk_output_ch_t enCh, const stc_clk_output_cfg_t *pstcOutputCfg);
|
|
void CLK_OutputClkCmd(en_clk_output_ch_t enCh, en_functional_state_t enNewState);
|
|
en_flag_status_t CLK_GetFlagStatus(en_clk_flag_t enClkFlag);
|
|
|
|
void CLK_FcmConfig(const stc_clk_fcm_cfg_t *pstcClkFcmCfg);
|
|
void CLK_FcmCmd(en_functional_state_t enNewState);
|
|
|
|
uint16_t CLK_GetFcmCounter(void);
|
|
en_flag_status_t CLK_GetFcmFlag(en_clk_fcm_flag_t enFcmFlag);
|
|
void CLK_ClearFcmFlag(en_clk_fcm_flag_t enFcmFlag);
|
|
|
|
void CLK_ClearXtalStdFlag(void);
|
|
|
|
//@} // CmuGroup
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
|
|
#endif /* DDL_CLK_ENABLE */
|
|
|
|
#endif /* __HC32F460_CLK_H__ */
|
|
|
|
/*******************************************************************************
|
|
* EOF (not truncated)
|
|
******************************************************************************/
|