mirror of
https://github.com/RT-Thread/rt-thread.git
synced 2025-01-20 22:43:32 +08:00
7528645f59
Changes: - added config for NEW_CTX_SWITCH - used new context on c906 sched switch routine - update _rt_hw_stack_init to fit into NEW_CTX_SWITCH - separated vector ctx from the generic Signed-off-by: Shell <smokewood@qq.com>
51 lines
1.5 KiB
C
51 lines
1.5 KiB
C
/*
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* Copyright (c) 2006-2022, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2022-10-10 RT-Thread the first version,
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* compatible to riscv-v-spec-1.0
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*/
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#ifndef __VECTOR_ENCODING_H__
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#define __VECTOR_ENCODING_H__
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/* mstatus/sstatus */
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#define MSTATUS_VS 0x00000600
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#define SSTATUS_VS 0x00000600 /* Vector Status */
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#define SSTATUS_VS_INITIAL 0x00000200
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#define SSTATUS_VS_CLEAN 0x00000400
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#define SSTATUS_VS_DIRTY 0x00000600
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/**
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* assembler names used for vset{i}vli vtypei immediate
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*/
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#define VEC_IMM_SEW_8 e8
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#define VEC_IMM_SEW_16 e16
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#define VEC_IMM_SEW_32 e32
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#define VEC_IMM_SEW_64 e64
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/* group setting, encoding by multiplier */
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#define VEC_IMM_LMUL_F8 mf8
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#define VEC_IMM_LMUL_F4 mf4
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#define VEC_IMM_LMUL_F2 mf2
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#define VEC_IMM_LMUL_1 m1
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#define VEC_IMM_LMUL_2 m2
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#define VEC_IMM_LMUL_4 m4
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#define VEC_IMM_LMUL_8 m8
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/* TAIL & MASK agnostic bits */
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#define VEC_IMM_TAIL_AGNOSTIC ta
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#define VEC_IMM_MASK_AGNOSTIC ma
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#define VEC_IMM_TAMA VEC_IMM_TAIL_AGNOSTIC, VEC_IMM_MASK_AGNOSTIC
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#define VEC_IMM_TAMU VEC_IMM_TAIL_AGNOSTIC
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#define VEC_IMM_TUMA VEC_IMM_MASK_AGNOSTIC
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/**
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* configuration setting instruction
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*/
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#define VEC_CONFIG_SETVLI(xVl, xAvl, vtype...) vsetvli xVl, xAvl, ##vtype
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#define VEC_CONFIG_SET_VL_VTYPE(xVl, xVtype) vsetvl x0, xVl, xVtype
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#endif /* __VECTOR_ENCODING_H__ */ |