379 lines
24 KiB
C
379 lines
24 KiB
C
/**************************************************************************//**
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* @file adc.h
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* @brief ADC driver header file
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*
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* SPDX-License-Identifier: Apache-2.0
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* @copyright (C) 2020~2021 Nuvoton Technology Corp. All rights reserved.
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*****************************************************************************/
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#ifndef __ADC_REG_H__
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#define __ADC_REG_H__
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#if defined ( __CC_ARM )
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#pragma anon_unions
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#endif
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/**
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@addtogroup REGISTER Control Register
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@{
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*/
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/**
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@addtogroup ADC Analog to Digital Converter(ADC)
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Memory Mapped Structure for ADC Controller
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@{ */
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typedef struct
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{
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/**
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* @var ADC_T::CTL
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* Offset: 0x00 ADC Control
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* ---------------------------------------------------------------------------------------------------
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* |Bits |Field |Descriptions
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* | :----: | :----: | :---- |
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* |[0] |ADEN |ADC Power Control
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* | | |0 = Power down ADC.
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* | | |1 = Power on ADC.
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* |[8] |MST |Menu Start Conversion
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* | | |0 = Functional menu not started.
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* | | |1 = Start all enable bit in ADC_CONF register.
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* | | |Note: This bit is set by software and cleared by hardware when all the tasks listed in ADC_CONF are done.
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* |[9] |PEDEEN |Pen Down Event Enable Bit
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* | | |0 = Pen down event interrupt Disabled.
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* | | |1 = Pen down event interrupt Enabled.
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* |[11] |WKTEN |Touch Wake Up Enable Bit
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* | | |0 = Touch wake-up Disabled.
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* | | |1 = Touch wake-up Enabled.
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* |[16] |WMSWCH |Wire Mode Switch for 5-wire/4-wire Configuration
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* | | |0 = 4-wire mode.
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* | | |1 = 5-wire mode.
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* @var ADC_T::CONF
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* Offset: 0x04 ADC Configure
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* ---------------------------------------------------------------------------------------------------
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* |Bits |Field |Descriptions
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* | :----: | :----: | :---- |
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* |[0] |TEN |Touch Detection Enable Bit
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* | | |0 = Touch detection function Disabled.
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* | | |1 = Touch detection function Enabled.
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* |[1] |ZEN |Press Measure Enable Bit
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* | | |1 = Press measure function Disabled.
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* | | |1 = Press measure function Enabled.
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* |[2] |NACEN |Normal A/D Conversion Enable Bit
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* | | |ADC normal conversion function enable
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* | | |0 = Normal A/D Conversion Disabled.
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* | | |1 = Normal A/D Conversion Enabled.
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* |[7:6] |REFSEL |ADC Reference Select
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* | | |ADC reference voltage select when ADC operate in normal conversion.
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* | | |00 = AGND33 vs VREF input.
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* | | |01 = YM vs YP.
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* | | |10 = XM vs XP.
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* | | |11 = AGND33 vs AVDD33.
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* |[14:12] |CHSEL |Channel Selection
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* | | |ADC input channel selection.
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* | | |000 = VREF.
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* | | |001 = A1.
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* | | |010 = A2.
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* | | |011 = VSENSE.
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* | | |100 = YM.
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* | | |101 = YP.
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* | | |110 = XM.
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* | | |111 = XP.
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* |[20] |TMAVDIS |Display T Mean Average Disable Bit
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* | | |Touch mean average for X and Y function disable bit.
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* | | |0 = Touch mean average for X and Y function Enabled.
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* | | |1 = Touch mean average for X and Y function Disabled.
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* |[21] |ZMAVDIS |Display Z Mean Average Disable Bit
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* | | |Pressure mean average for Z1 and Z2 function disable bit.
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* | | |0 = Pressure mean average for Z1 and Z2 function Enabled.
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* | | |1 = Pressure mean average for Z1 and Z2 function Disabled.
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* |[22] |SPEED |Speed Mode Selection
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* | | |0 = All ADC channels set to high speed mode.
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* | | |1 = All ADC channels set to low speed mode.
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* @var ADC_T::IER
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* Offset: 0x08 ADC Interrupt Enable Register
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* ---------------------------------------------------------------------------------------------------
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* |Bits |Field |Descriptions
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* | :----: | :----: | :---- |
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* |[0] |MIEN |Menu Interrupt Enable Bit
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* | | |Function menu complete interrupt enable.
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* | | |0 = Menu interrupt Disabled.
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* | | |1 = Menu interrupt Enabled.
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* |[2] |PEDEIEN |Pen Down Event Interrupt Enable Bit
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* | | |0 = Pen down event detection interrupt Disabled.
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* | | |1 = Pen down event detection interrupt Enabled.
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* |[3] |WKTIEN |Wake Up Touch Interrupt Enable Bit
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* | | |0 = Wake up touch detection interrupt Disabled.
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* | | |1 = Wake up touch detection interrupt Enabled.
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* |[6] |PEUEIEN |Pen Up Event Interrupt Enable Bit
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* | | |0 = Pen up event detection interrupt Disabled.
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* | | |1 = Pen up event detection interrupt Enabled.
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* @var ADC_T::ISR
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* Offset: 0x0C ADC Interrupt Status Register
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* ---------------------------------------------------------------------------------------------------
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* |Bits |Field |Descriptions
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* | :----: | :----: | :---- |
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* |[0] |MF |Menu Complete Flag
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* | | |Function menu complete status indicator.
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* | | |Note: Set by hardware and write 1 to clear this bit.
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* |[2] |PEDEF |Pen Down Event Flag
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* | | |Pen down event status indicator.
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* | | |Note: Set by hardware and write 1 to clear this bit.
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* |[4] |PEUEF |Pen Up Event Flag
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* | | |Pen up event status indicator.
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* | | |Note: Set by hardware and write 1 to clear this bit.
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* |[8] |TF |Touch Conversion Finish
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* | | |Functional menu touch detection conversion finish.
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* | | |Note: Set by hardware and write 1 to clear this bit.
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* |[9] |ZF |Press Conversion Finish
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* | | |Functional menu press measure conversion finish.
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* | | |Note: Set by hardware and write 1 to clear this bit.
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* |[10] |NACF |Normal AD Conversion Finish
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* | | |Functional menu normal AD conversion finish.
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* | | |Note: Set by hardware and write 1 to clear this bit.
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* |[17] |INTTC |Interrupt Signal for Touch Screen Touching Detection
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* | | |This signal is directly from analog macro without de-bouncing and can be used to determine the pen down touch event together with PEDEF (ADC_ISR[2]) flag.
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* @var ADC_T::WKISR
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* Offset: 0x10 ADC Wake-up interrupt Status Register
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* ---------------------------------------------------------------------------------------------------
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* |Bits |Field |Descriptions
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* | :----: | :----: | :---- |
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* |[1] |WPEDEF |Wake Up Pen Down Event Flag
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* | | |Pen down event wake up status indicator.
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* @var ADC_T::XYDATA
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* Offset: 0x20 ADC Touch X,Y Position Data
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* ---------------------------------------------------------------------------------------------------
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* |Bits |Field |Descriptions
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* | :----: | :----: | :---- |
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* |[11:0] |XDATA |ADC X Data
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* | | |When TEN (ADC_CONF[0]) is set, the touch x-position will be stored in this register.
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* | | |Note: If the TMAVDIS (ADC_CONF[20]) = 0, both x and y position are the results of the mean average of x and y in ADC_XYSORT0 ~ ADC_XYSORT3.
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* |[27:16] |YDATA |ADC Y Data
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* | | |When TEN (ADC_CONF[0]) is set, the touch y-position will be stored in this register.
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* | | |Note: If the TMAVDIS (ADC_CONF[20]) = 0, both x and y position are the results of the mean average of x and y in ADC_XYSORT0 ~ ADC_XYSORT3.
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* @var ADC_T::ZDATA
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* Offset: 0x24 ADC Touch Z Pressure Data
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* ---------------------------------------------------------------------------------------------------
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* |Bits |Field |Descriptions
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* | :----: | :----: | :---- |
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* |[11:0] |Z1DATA |ADC Z1 Data
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* | | |When ZEN (ADC_CONF[1]) is set; the touch pressure measure Z1 will be stored in this register.
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* | | |Note: If the ZMAVDIS (ADC_CONF[21]) = 0, both Z1 and Z2 data is the results of the mean average of Z1 and Z2 in ADC_ZSORT0 ~ ADC_ZSORT3.
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* |[27:16] |Z2DATA |ADC Z2 Data
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* | | |When ZEN (ADC_CONF[1]) is set; the touch pressure measure Z2 will be stored in this register.
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* | | |Note: If the ZMAVDIS (ADC_CONF[21]) = 0, both Z1 and Z2 data is the results of the mean average of Z1 and Z2 in ADC_ZSORT0 ~ ADC_ZSORT3.
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* @var ADC_T::DATA
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* Offset: 0x28 ADC Normal Conversion Data
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* ---------------------------------------------------------------------------------------------------
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* |Bits |Field |Descriptions
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* | :----: | :----: | :---- |
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* |[11:0] |ADCDATA |ADC Data
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* | | |When NACEN (ADC_CONF[2]) is enabled, the AD converting result with corresponding channel is stored in this register.
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* @var ADC_T::XYSORT0
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* Offset: 0x1F4 ADC Touch XY Position Mean Value Sort 0
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* ---------------------------------------------------------------------------------------------------
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* |Bits |Field |Descriptions
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* | :----: | :----: | :---- |
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* |[11:0] |XSORT0 |X Position Sort Data 0
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* | | |X position mean average sort data 0.
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* |[27:16] |YSORT0 |Y Position Sort Data 0
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* | | |Y position mean average sort data 0.
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* @var ADC_T::XYSORT1
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* Offset: 0x1F8 ADC Touch XY Position Mean Value Sort 1
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* ---------------------------------------------------------------------------------------------------
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* |Bits |Field |Descriptions
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* | :----: | :----: | :---- |
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* |[11:0] |XSORT1 |X Position Sort Data 1
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* | | |X position mean average sort data 1.
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* |[27:16] |YSORT1 |Y Position Sort Data 1
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* | | |Y position mean average sort data 1.
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* @var ADC_T::XYSORT2
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* Offset: 0x1FC ADC Touch XY Position Mean Value Sort 2
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* ---------------------------------------------------------------------------------------------------
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* |Bits |Field |Descriptions
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* | :----: | :----: | :---- |
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* |[11:0] |XSORT2 |X Position Sort Data 2
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* | | |X position mean average sort data 2.
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* |[27:16] |YSORT2 |Y Position Sort Data 2
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* | | |Y position mean average sort data 2.
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* @var ADC_T::XYSORT3
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* Offset: 0x200 ADC Touch XY Position Mean Value Sort 3
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* ---------------------------------------------------------------------------------------------------
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* |Bits |Field |Descriptions
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* | :----: | :----: | :---- |
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* |[11:0] |XSORT3 |X Position Sort Data 3
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* | | |X position mean average sort data 3.
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* |[27:16] |YSORT3 |Y Position Sort Data 3
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* | | |Y position mean average sort data 3.
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* @var ADC_T::ZSORT0
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* Offset: 0x204 ADC Touch Z Pressure Mean Value Sort 0
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* ---------------------------------------------------------------------------------------------------
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* |Bits |Field |Descriptions
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* | :----: | :----: | :---- |
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* |[11:0] |Z1SORT0 |Z1 Position Sort Data 0
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* | | |Z1 position Mean average sort data 0.
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* |[27:16] |Z2SORT0 |Z2 Position Sort Data 0
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* | | |Z2 position Mean average sort data 0.
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* @var ADC_T::ZSORT1
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* Offset: 0x208 ADC Touch Z Pressure Mean Value Sort 1
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* ---------------------------------------------------------------------------------------------------
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* |Bits |Field |Descriptions
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* | :----: | :----: | :---- |
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* |[11:0] |Z1SORT1 |Z1 Position Sort Data 1
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* | | |Z1 position Mean average sort data 1.
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* |[27:16] |Z2SORT1 |Z2 Position Sort Data 1
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* | | |Z2 position Mean average sort data 1.
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* @var ADC_T::ZSORT2
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* Offset: 0x20C ADC Touch Z Pressure Mean Value Sort 2
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* ---------------------------------------------------------------------------------------------------
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* |Bits |Field |Descriptions
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* | :----: | :----: | :---- |
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* |[11:0] |Z1SORT2 |Z1 Position Sort Data 2
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* | | |Z1 position Mean average sort data 2.
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* |[27:16] |Z2SORT2 |Z2 Position Sort Data 2
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* | | |Z2 position Mean average sort data 2.
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* @var ADC_T::ZSORT3
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* Offset: 0x210 ADC Touch Z Pressure Mean Value Sort 3
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* ---------------------------------------------------------------------------------------------------
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* |Bits |Field |Descriptions
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* | :----: | :----: | :---- |
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* |[11:0] |Z1SORT3 |Z1 Position Sort Data 3
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* | | |Z1 position Mean average sort data 3.
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* |[27:16] |Z2SORT3 |Z2 Position Sort Data 3
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* | | |Z2 position Mean average sort data 3.
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*/
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__IO uint32_t CTL; /*!< [0x0000] ADC Control */
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__IO uint32_t CONF; /*!< [0x0004] ADC Configure */
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__IO uint32_t IER; /*!< [0x0008] ADC Interrupt Enable Register */
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__IO uint32_t ISR; /*!< [0x000c] ADC Interrupt Status Register */
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__I uint32_t WKISR; /*!< [0x0010] ADC Wake-up interrupt Status Register */
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__I uint32_t RESERVE0[3];
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__I uint32_t XYDATA; /*!< [0x0020] ADC Touch X,Y Position Data */
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__I uint32_t ZDATA; /*!< [0x0024] ADC Touch Z Pressure Data */
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__I uint32_t DATA; /*!< [0x0028] ADC Normal Conversion Data */
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__I uint32_t RESERVE1[114];
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__I uint32_t XYSORT[4]; /*!< [0x01f4~0x0200] ADC Touch XY Position Mean Value Sort Register */
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__I uint32_t ZSORT0[4]; /*!< [0x0204~0x0210] ADC Touch Z Pressure Mean Value Sort Register */
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} ADC_T;
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/**
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@addtogroup ADC_CONST ADC Bit Field Definition
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Constant Definitions for ADC Controller
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@{ */
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#define ADC_CTL_ADEN_Pos (0) /*!< ADC_T::CTL: ADEN Position */
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#define ADC_CTL_ADEN_Msk (0x1ul << ADC_CTL_ADEN_Pos) /*!< ADC_T::CTL: ADEN Mask */
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#define ADC_CTL_MST_Pos (8) /*!< ADC_T::CTL: MST Position */
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#define ADC_CTL_MST_Msk (0x1ul << ADC_CTL_MST_Pos) /*!< ADC_T::CTL: MST Mask */
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#define ADC_CTL_PEDEEN_Pos (9) /*!< ADC_T::CTL: PEDEEN Position */
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#define ADC_CTL_PEDEEN_Msk (0x1ul << ADC_CTL_PEDEEN_Pos) /*!< ADC_T::CTL: PEDEEN Mask */
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#define ADC_CTL_WKTEN_Pos (11) /*!< ADC_T::CTL: WKTEN Position */
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#define ADC_CTL_WKTEN_Msk (0x1ul << ADC_CTL_WKTEN_Pos) /*!< ADC_T::CTL: WKTEN Mask */
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#define ADC_CTL_WMSWCH_Pos (16) /*!< ADC_T::CTL: WMSWCH Position */
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#define ADC_CTL_WMSWCH_Msk (0x1ul << ADC_CTL_WMSWCH_Pos) /*!< ADC_T::CTL: WMSWCH Mask */
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#define ADC_CONF_TEN_Pos (0) /*!< ADC_T::CONF: TEN Position */
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#define ADC_CONF_TEN_Msk (0x1ul << ADC_CONF_TEN_Pos) /*!< ADC_T::CONF: TEN Mask */
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#define ADC_CONF_ZEN_Pos (1) /*!< ADC_T::CONF: ZEN Position */
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#define ADC_CONF_ZEN_Msk (0x1ul << ADC_CONF_ZEN_Pos) /*!< ADC_T::CONF: ZEN Mask */
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#define ADC_CONF_NACEN_Pos (2) /*!< ADC_T::CONF: NACEN Position */
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#define ADC_CONF_NACEN_Msk (0x1ul << ADC_CONF_NACEN_Pos) /*!< ADC_T::CONF: NACEN Mask */
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#define ADC_CONF_REFSEL_Pos (6) /*!< ADC_T::CONF: REFSEL Position */
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#define ADC_CONF_REFSEL_Msk (0x3ul << ADC_CONF_REFSEL_Pos) /*!< ADC_T::CONF: REFSEL Mask */
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#define ADC_CONF_CHSEL_Pos (12) /*!< ADC_T::CONF: CHSEL Position */
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#define ADC_CONF_CHSEL_Msk (0x7ul << ADC_CONF_CHSEL_Pos) /*!< ADC_T::CONF: CHSEL Mask */
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#define ADC_CONF_TMAVDIS_Pos (20) /*!< ADC_T::CONF: TMAVDIS Position */
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#define ADC_CONF_TMAVDIS_Msk (0x1ul << ADC_CONF_TMAVDIS_Pos) /*!< ADC_T::CONF: TMAVDIS Mask */
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#define ADC_CONF_ZMAVDIS_Pos (21) /*!< ADC_T::CONF: ZMAVDIS Position */
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#define ADC_CONF_ZMAVDIS_Msk (0x1ul << ADC_CONF_ZMAVDIS_Pos) /*!< ADC_T::CONF: ZMAVDIS Mask */
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#define ADC_CONF_SPEED_Pos (22) /*!< ADC_T::CONF: SPEED Position */
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#define ADC_CONF_SPEED_Msk (0x1ul << ADC_CONF_SPEED_Pos) /*!< ADC_T::CONF: SPEED Mask */
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#define ADC_IER_MIEN_Pos (0) /*!< ADC_T::IER: MIEN Position */
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#define ADC_IER_MIEN_Msk (0x1ul << ADC_IER_MIEN_Pos) /*!< ADC_T::IER: MIEN Mask */
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#define ADC_IER_PEDEIEN_Pos (2) /*!< ADC_T::IER: PEDEIEN Position */
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#define ADC_IER_PEDEIEN_Msk (0x1ul << ADC_IER_PEDEIEN_Pos) /*!< ADC_T::IER: PEDEIEN Mask */
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#define ADC_IER_WKTIEN_Pos (3) /*!< ADC_T::IER: WKTIEN Position */
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#define ADC_IER_WKTIEN_Msk (0x1ul << ADC_IER_WKTIEN_Pos) /*!< ADC_T::IER: WKTIEN Mask */
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#define ADC_IER_PEUEIEN_Pos (6) /*!< ADC_T::IER: PEUEIEN Position */
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#define ADC_IER_PEUEIEN_Msk (0x1ul << ADC_IER_PEUEIEN_Pos) /*!< ADC_T::IER: PEUEIEN Mask */
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#define ADC_ISR_MF_Pos (0) /*!< ADC_T::ISR: MF Position */
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#define ADC_ISR_MF_Msk (0x1ul << ADC_ISR_MF_Pos) /*!< ADC_T::ISR: MF Mask */
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#define ADC_ISR_PEDEF_Pos (2) /*!< ADC_T::ISR: PEDEF Position */
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#define ADC_ISR_PEDEF_Msk (0x1ul << ADC_ISR_PEDEF_Pos) /*!< ADC_T::ISR: PEDEF Mask */
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#define ADC_ISR_PEUEF_Pos (4) /*!< ADC_T::ISR: PEUEF Position */
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#define ADC_ISR_PEUEF_Msk (0x1ul << ADC_ISR_PEUEF_Pos) /*!< ADC_T::ISR: PEUEF Mask */
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#define ADC_ISR_TF_Pos (8) /*!< ADC_T::ISR: TF Position */
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#define ADC_ISR_TF_Msk (0x1ul << ADC_ISR_TF_Pos) /*!< ADC_T::ISR: TF Mask */
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#define ADC_ISR_ZF_Pos (9) /*!< ADC_T::ISR: ZF Position */
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#define ADC_ISR_ZF_Msk (0x1ul << ADC_ISR_ZF_Pos) /*!< ADC_T::ISR: ZF Mask */
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#define ADC_ISR_NACF_Pos (10) /*!< ADC_T::ISR: NACF Position */
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#define ADC_ISR_NACF_Msk (0x1ul << ADC_ISR_NACF_Pos) /*!< ADC_T::ISR: NACF Mask */
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#define ADC_ISR_INTTC_Pos (17) /*!< ADC_T::ISR: INTTC Position */
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#define ADC_ISR_INTTC_Msk (0x1ul << ADC_ISR_INTTC_Pos) /*!< ADC_T::ISR: INTTC Mask */
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#define ADC_WKISR_WPEDEF_Pos (1) /*!< ADC_T::WKISR: WPEDEF Position */
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#define ADC_WKISR_WPEDEF_Msk (0x1ul << ADC_WKISR_WPEDEF_Pos) /*!< ADC_T::WKISR: WPEDEF Mask */
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#define ADC_XYDATA_XDATA_Pos (0) /*!< ADC_T::XYDATA: XDATA Position */
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#define ADC_XYDATA_XDATA_Msk (0xffful << ADC_XYDATA_XDATA_Pos) /*!< ADC_T::XYDATA: XDATA Mask */
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#define ADC_XYDATA_YDATA_Pos (16) /*!< ADC_T::XYDATA: YDATA Position */
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#define ADC_XYDATA_YDATA_Msk (0xffful << ADC_XYDATA_YDATA_Pos) /*!< ADC_T::XYDATA: YDATA Mask */
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#define ADC_ZDATA_Z1DATA_Pos (0) /*!< ADC_T::ZDATA: Z1DATA Position */
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#define ADC_ZDATA_Z1DATA_Msk (0xffful << ADC_ZDATA_Z1DATA_Pos) /*!< ADC_T::ZDATA: Z1DATA Mask */
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#define ADC_ZDATA_Z2DATA_Pos (16) /*!< ADC_T::ZDATA: Z2DATA Position */
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#define ADC_ZDATA_Z2DATA_Msk (0xffful << ADC_ZDATA_Z2DATA_Pos) /*!< ADC_T::ZDATA: Z2DATA Mask */
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#define ADC_DATA_ADCDATA_Pos (0) /*!< ADC_T::DATA: ADCDATA Position */
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#define ADC_DATA_ADCDATA_Msk (0xffful << ADC_DATA_ADCDATA_Pos) /*!< ADC_T::DATA: ADCDATA Mask */
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#define ADC_XYSORT_XSORT_Pos (0) /*!< ADC_T::XYSORT: XSORT Position */
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#define ADC_XYSORT_XSORT_Msk (0xffful << ADC_XYSORT_XSORT_Pos) /*!< ADC_T::XYSORT: XSORT Mask */
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#define ADC_XYSORT_YSORT_Pos (16) /*!< ADC_T::XYSORT: YSORT Position */
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#define ADC_XYSORT_YSORT_Msk (0xffful << ADC_XYSORT_YSORT_Pos) /*!< ADC_T::XYSORT: YSORT Mask */
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#define ADC_ZSORT_Z1SORT_Pos (0) /*!< ADC_T::ZSORT: Z1SORT Position */
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#define ADC_ZSORT_Z1SORT_Msk (0xffful << ADC_ZSORT_Z1SORT_Pos) /*!< ADC_T::ZSORT: Z1SORT Mask */
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#define ADC_ZSORT_Z2SORT_Pos (16) /*!< ADC_T::ZSORT: Z2SORT Position */
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#define ADC_ZSORT_Z2SORT_Msk (0xffful << ADC_ZSORT_Z2SORT_Pos) /*!< ADC_T::ZSORT: Z2SORT Mask */
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/**@}*/ /* ADC_CONST */
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/**@}*/ /* end of ADC register group */
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/**@}*/ /* end of REGISTER group */
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#if defined ( __CC_ARM )
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#pragma no_anon_unions
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#endif
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#endif //__ADC_REG_H__
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