166 lines
4.9 KiB
C
166 lines
4.9 KiB
C
/*
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* Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2022-04-28 CDT first version
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*/
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#include "board.h"
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#include "board_config.h"
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/* unlock/lock peripheral */
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#define EXAMPLE_PERIPH_WE (LL_PERIPH_GPIO | LL_PERIPH_EFM | LL_PERIPH_FCG | \
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LL_PERIPH_PWC_CLK_RMU | LL_PERIPH_SRAM)
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#define EXAMPLE_PERIPH_WP (LL_PERIPH_EFM | LL_PERIPH_FCG | LL_PERIPH_SRAM)
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#if defined(BSP_USING_USBD) || defined(BSP_USING_USBH)
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/**
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* @brief Switch clock stable time
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* @note Approx. 30us
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*/
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#define CLK_SYSCLK_SW_STB (HCLK_VALUE / 50000UL)
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/**
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* @brief Clk delay function
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* @param [in] u32Delay count
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* @retval when switch clock source, should be delay some time to wait stable.
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*/
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static void CLK_Delay(uint32_t u32Delay)
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{
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__IO uint32_t u32Timeout = 0UL;
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while (u32Timeout < u32Delay)
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{
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u32Timeout++;
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}
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}
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#endif
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/** System Base Configuration
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*/
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void SystemBase_Config(void)
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{
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#if defined(BSP_USING_ON_CHIP_FLASH_ICODE_CACHE)
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EFM_ICacheCmd(ENABLE);
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#endif
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#if defined(BSP_USING_ON_CHIP_FLASH_DCODE_CACHE)
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EFM_DCacheCmd(ENABLE);
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#endif
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#if defined(BSP_USING_ON_CHIP_FLASH_ICODE_PREFETCH)
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EFM_PrefetchCmd(ENABLE);
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#endif
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/* Reset the VBAT area */
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PWC_VBAT_Reset();
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}
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/** System Clock Configuration
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*/
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void SystemClock_Config(void)
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{
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stc_clock_xtal_init_t stcXtalInit;
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stc_clock_pll_init_t stcPLLHInit;
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#if defined(BSP_USING_USBD) || defined(BSP_USING_USBH)
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stc_clock_pllx_init_t stcPLLAInit;
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#endif
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#if defined(BSP_RTC_USING_XTAL32) || defined(RT_USING_PM)
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stc_clock_xtal32_init_t stcXtal32Init;
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#endif
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/* PCLK0, HCLK Max 240MHz */
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/* PCLK1, PCLK4 Max 120MHz */
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/* PCLK2, PCLK3 Max 60MHz */
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/* EX BUS Max 120MHz */
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CLK_SetClockDiv(CLK_BUS_CLK_ALL, \
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(CLK_PCLK0_DIV1 | CLK_PCLK1_DIV2 | CLK_PCLK2_DIV4 | \
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CLK_PCLK3_DIV4 | CLK_PCLK4_DIV2 | CLK_EXCLK_DIV2 | \
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CLK_HCLK_DIV1));
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GPIO_AnalogCmd(XTAL_PORT, XTAL_IN_PIN | XTAL_OUT_PIN, ENABLE);
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(void)CLK_XtalStructInit(&stcXtalInit);
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/* Config Xtal and enable Xtal */
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stcXtalInit.u8Mode = CLK_XTAL_MD_OSC;
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stcXtalInit.u8Drv = CLK_XTAL_DRV_ULOW;
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stcXtalInit.u8State = CLK_XTAL_ON;
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stcXtalInit.u8StableTime = CLK_XTAL_STB_2MS;
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(void)CLK_XtalInit(&stcXtalInit);
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(void)CLK_PLLStructInit(&stcPLLHInit);
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/* VCO = (8/1)*120 = 960MHz*/
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stcPLLHInit.u8PLLState = CLK_PLL_ON;
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stcPLLHInit.PLLCFGR = 0UL;
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stcPLLHInit.PLLCFGR_f.PLLM = 1UL - 1UL;
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stcPLLHInit.PLLCFGR_f.PLLN = 120UL - 1UL;
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stcPLLHInit.PLLCFGR_f.PLLP = 4UL - 1UL;
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stcPLLHInit.PLLCFGR_f.PLLQ = 4UL - 1UL;
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stcPLLHInit.PLLCFGR_f.PLLR = 4UL - 1UL;
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stcPLLHInit.PLLCFGR_f.PLLSRC = CLK_PLL_SRC_XTAL;
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(void)CLK_PLLInit(&stcPLLHInit);
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/* Highspeed SRAM set to 0 Read/Write wait cycle */
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SRAM_SetWaitCycle(SRAM_SRAMH, SRAM_WAIT_CYCLE0, SRAM_WAIT_CYCLE0);
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/* SRAM1_2_3_4_backup set to 1 Read/Write wait cycle */
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SRAM_SetWaitCycle((SRAM_SRAM123 | SRAM_SRAM4 | SRAM_SRAMB), SRAM_WAIT_CYCLE1, SRAM_WAIT_CYCLE1);
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/* 0-wait @ 40MHz */
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(void)EFM_SetWaitCycle(EFM_WAIT_CYCLE5);
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/* 4 cycles for 200 ~ 250MHz */
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GPIO_SetReadWaitCycle(GPIO_RD_WAIT4);
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CLK_SetSysClockSrc(CLK_SYSCLK_SRC_PLL);
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#if defined(BSP_USING_USBD) || defined(BSP_USING_USBH)
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/* PLLX for USB */
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(void)CLK_PLLxStructInit(&stcPLLAInit);
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/* VCO = (8/2)*120 = 480MHz*/
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stcPLLAInit.u8PLLState = CLK_PLL_ON;
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stcPLLAInit.PLLCFGR = 0UL;
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stcPLLAInit.PLLCFGR_f.PLLM = 2UL - 1UL;
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stcPLLAInit.PLLCFGR_f.PLLN = 120UL - 1UL;
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stcPLLAInit.PLLCFGR_f.PLLP = 10UL - 1UL;
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stcPLLAInit.PLLCFGR_f.PLLQ = 4UL - 1UL;
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stcPLLAInit.PLLCFGR_f.PLLR = 4UL - 1UL;
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(void)CLK_PLLxInit(&stcPLLAInit);
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#endif
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#if defined(BSP_RTC_USING_XTAL32) || defined(RT_USING_PM)
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/* Xtal32 config */
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GPIO_AnalogCmd(XTAL32_PORT, XTAL32_IN_PIN | XTAL32_OUT_PIN, ENABLE);
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(void)CLK_Xtal32StructInit(&stcXtal32Init);
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stcXtal32Init.u8State = CLK_XTAL32_ON;
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stcXtal32Init.u8Drv = CLK_XTAL32_DRV_HIGH;
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stcXtal32Init.u8Filter = CLK_XTAL32_FILTER_RUN_MD;
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(void)CLK_Xtal32Init(&stcXtal32Init);
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#endif
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}
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/** Peripheral Clock Configuration
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*/
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void PeripheralClock_Config(void)
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{
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#if defined(BSP_USING_CAN1)
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CLK_SetCANClockSrc(CLK_CAN1, CLK_CANCLK_SYSCLK_DIV6);
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#endif
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#if defined(BSP_USING_CAN2)
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CLK_SetCANClockSrc(CLK_CAN2, CLK_CANCLK_SYSCLK_DIV6);
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#endif
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#if defined(RT_USING_ADC)
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CLK_SetPeriClockSrc(CLK_PERIPHCLK_PCLK);
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#endif
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#if defined(BSP_USING_USBD) || defined(BSP_USING_USBH)
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CLK_SetUSBClockSrc(CLK_USBCLK_PLLXP);
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/* Wait stable here, since the current DDL API does not include this */
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CLK_Delay(CLK_SYSCLK_SW_STB);
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#endif
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}
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/** Peripheral Registers Unlock
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*/
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void PeripheralRegister_Unlock(void)
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{
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LL_PERIPH_WE(EXAMPLE_PERIPH_WE);
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}
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/*@}*/
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