494 lines
14 KiB
C
494 lines
14 KiB
C
/*
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* Copyright (c) 2006-2023, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2017-10-10 Tanek first version
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*/
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#include <rtthread.h>
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#include <rthw.h>
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#include <drivers/dev_mmcsd_core.h>
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#include <board.h>
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#include <fsl_usdhc.h>
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#include <fsl_gpio.h>
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#include <fsl_iomuxc.h>
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#include <finsh.h>
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#define RT_USING_SDIO1
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#define RT_USING_SDIO2
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//#define DEBUG
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#ifdef DEBUG
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static int enable_log = 1;
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#define MMCSD_DGB(fmt, ...) \
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do \
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{ \
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if (enable_log) \
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{ \
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rt_kprintf(fmt, ##__VA_ARGS__); \
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} \
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} while (0)
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#else
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#define MMCSD_DGB(fmt, ...)
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#endif
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#define CACHE_LINESIZE (32)
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#define IMXRT_MAX_FREQ (25UL * 1000UL * 1000UL)
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#define USDHC_READ_BURST_LEN (8U) /*!< number of words USDHC read in a single burst */
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#define USDHC_WRITE_BURST_LEN (8U) /*!< number of words USDHC write in a single burst */
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#define USDHC_DATA_TIMEOUT (0xFU) /*!< data timeout counter value */
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#define SDMMCHOST_SUPPORT_MAX_BLOCK_LENGTH (4096U)
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#define SDMMCHOST_SUPPORT_MAX_BLOCK_COUNT (USDHC_MAX_BLOCK_COUNT)
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/* Read/write watermark level. The bigger value indicates DMA has higher read/write performance. */
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#define USDHC_READ_WATERMARK_LEVEL (0x80U)
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#define USDHC_WRITE_WATERMARK_LEVEL (0x80U)
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/* DMA mode */
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#define USDHC_DMA_MODE kUSDHC_DmaModeAdma2
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/* Endian mode. */
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#define USDHC_ENDIAN_MODE kUSDHC_EndianModeLittle
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//#ifdef SOC_IMXRT1170_SERIES
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#define USDHC_ADMA_TABLE_WORDS (32U) /* define the ADMA descriptor table length */
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#define USDHC_ADMA2_ADDR_ALIGN (4U) /* define the ADMA2 descriptor table addr align size */
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//#else
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//#define USDHC_ADMA_TABLE_WORDS (8U) /* define the ADMA descriptor table length */
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//#define USDHC_ADMA2_ADDR_ALIGN (4U) /* define the ADMA2 descriptor table addr align size */
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//#endif
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//rt_align(USDHC_ADMA2_ADDR_ALIGN) uint32_t g_usdhcAdma2Table[USDHC_ADMA_TABLE_WORDS] SECTION("NonCacheable");
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AT_NONCACHEABLE_SECTION_ALIGN(uint32_t g_usdhcAdma2Table[USDHC_ADMA_TABLE_WORDS], USDHC_ADMA2_ADDR_ALIGN);
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struct imxrt_mmcsd
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{
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struct rt_mmcsd_host *host;
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struct rt_mmcsd_req *req;
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struct rt_mmcsd_cmd *cmd;
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struct rt_timer timer;
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rt_uint32_t *buf;
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//USDHC_Type *base;
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usdhc_host_t usdhc_host;
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#ifndef SOC_IMXRT1170_SERIES
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clock_div_t usdhc_div;
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#endif
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clock_ip_name_t ip_clock;
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uint32_t *usdhc_adma2_table;
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};
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#ifndef CODE_STORED_ON_SDCARD
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static void _mmcsd_gpio_init(struct imxrt_mmcsd *mmcsd)
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{
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// CLOCK_EnableClock(kCLOCK_Iomuxc); /* iomuxc clock (iomuxc_clk_enable): 0x03u */
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}
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#endif
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static void SDMMCHOST_ErrorRecovery(USDHC_Type *base)
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{
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uint32_t status = 0U;
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/* get host present status */
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status = USDHC_GetPresentStatusFlags(base);
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/* check command inhibit status flag */
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if ((status & kUSDHC_CommandInhibitFlag) != 0U)
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{
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/* reset command line */
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USDHC_Reset(base, kUSDHC_ResetCommand, 1000U);
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}
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/* check data inhibit status flag */
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if ((status & kUSDHC_DataInhibitFlag) != 0U)
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{
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/* reset data line */
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USDHC_Reset(base, kUSDHC_ResetData, 1000U);
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}
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}
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#ifndef CODE_STORED_ON_SDCARD
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static void _mmcsd_host_init(struct imxrt_mmcsd *mmcsd)
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{
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usdhc_host_t *usdhc_host = &mmcsd->usdhc_host;
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/* Initializes SDHC. */
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usdhc_host->config.dataTimeout = USDHC_DATA_TIMEOUT;
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usdhc_host->config.endianMode = USDHC_ENDIAN_MODE;
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usdhc_host->config.readWatermarkLevel = USDHC_READ_WATERMARK_LEVEL;
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usdhc_host->config.writeWatermarkLevel = USDHC_WRITE_WATERMARK_LEVEL;
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#if !(defined(FSL_FEATURE_USDHC_HAS_NO_RW_BURST_LEN) && FSL_FEATURE_USDHC_HAS_NO_RW_BURST_LEN)
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usdhc_host->config.readBurstLen = USDHC_READ_BURST_LEN;
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usdhc_host->config.writeBurstLen = USDHC_WRITE_BURST_LEN;
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#endif
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USDHC_Init(usdhc_host->base, &(usdhc_host->config));
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}
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static void _mmcsd_clk_init(struct imxrt_mmcsd *mmcsd)
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{
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CLOCK_EnableClock(mmcsd->ip_clock);
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#if !defined(SOC_IMXRT1170_SERIES) && !defined(SOC_MIMXRT1062DVL6A)
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CLOCK_SetDiv(mmcsd->usdhc_div, 5U);
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#endif
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}
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static void _mmcsd_isr_init(struct imxrt_mmcsd *mmcsd)
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{
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//NVIC_SetPriority(USDHC1_IRQn, 5U);
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}
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#endif
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static void _mmc_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req)
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{
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struct imxrt_mmcsd *mmcsd;
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struct rt_mmcsd_cmd *cmd;
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struct rt_mmcsd_data *data;
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status_t error;
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usdhc_adma_config_t dmaConfig;
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usdhc_transfer_t fsl_content = {0};
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usdhc_command_t fsl_command = {0};
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usdhc_data_t fsl_data = {0};
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rt_uint32_t *buf = NULL;
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RT_ASSERT(host != RT_NULL);
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RT_ASSERT(req != RT_NULL);
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mmcsd = (struct imxrt_mmcsd *)host->private_data;
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RT_ASSERT(mmcsd != RT_NULL);
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cmd = req->cmd;
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RT_ASSERT(cmd != RT_NULL);
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MMCSD_DGB("\tcmd->cmd_code: %02d, cmd->arg: %08x, cmd->flags: %08x --> ", cmd->cmd_code, cmd->arg, cmd->flags);
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data = cmd->data;
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rt_memset(&dmaConfig, 0, sizeof(usdhc_adma_config_t));
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/* config adma */
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dmaConfig.dmaMode = USDHC_DMA_MODE;
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#if !(defined(FSL_FEATURE_USDHC_HAS_NO_RW_BURST_LEN) && FSL_FEATURE_USDHC_HAS_NO_RW_BURST_LEN)
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dmaConfig.burstLen = kUSDHC_EnBurstLenForINCR;
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#endif
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dmaConfig.admaTable = mmcsd->usdhc_adma2_table;
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dmaConfig.admaTableWords = USDHC_ADMA_TABLE_WORDS;
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fsl_command.index = cmd->cmd_code;
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fsl_command.argument = cmd->arg;
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if (cmd->cmd_code == STOP_TRANSMISSION)
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fsl_command.type = kCARD_CommandTypeAbort;
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else
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fsl_command.type = kCARD_CommandTypeNormal;
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switch (cmd->flags & RESP_MASK)
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{
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case RESP_NONE:
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fsl_command.responseType = kCARD_ResponseTypeNone;
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break;
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case RESP_R1:
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fsl_command.responseType = kCARD_ResponseTypeR1;
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break;
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case RESP_R1B:
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fsl_command.responseType = kCARD_ResponseTypeR1b;
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break;
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case RESP_R2:
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fsl_command.responseType = kCARD_ResponseTypeR2;
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break;
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case RESP_R3:
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fsl_command.responseType = kCARD_ResponseTypeR3;
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break;
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case RESP_R4:
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fsl_command.responseType = kCARD_ResponseTypeR4;
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break;
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case RESP_R6:
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fsl_command.responseType = kCARD_ResponseTypeR6;
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break;
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case RESP_R7:
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fsl_command.responseType = kCARD_ResponseTypeR7;
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break;
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case RESP_R5:
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fsl_command.responseType = kCARD_ResponseTypeR5;
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break;
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default:
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RT_ASSERT(NULL);
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}
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fsl_command.flags = 0;
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fsl_content.command = &fsl_command;
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if (data)
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{
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if (req->stop != NULL)
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fsl_data.enableAutoCommand12 = true;
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else
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fsl_data.enableAutoCommand12 = false;
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fsl_data.enableAutoCommand23 = false;
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fsl_data.enableIgnoreError = false;
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fsl_data.dataType = kUSDHC_TransferDataNormal; //todo : update data type
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fsl_data.blockSize = data->blksize;
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fsl_data.blockCount = data->blks;
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MMCSD_DGB(" blksize:%d, blks:%d ", fsl_data.blockSize, fsl_data.blockCount);
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if (((rt_uint32_t)data->buf & (CACHE_LINESIZE - 1)) || // align cache(32byte)
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((rt_uint32_t)data->buf > 0x00000000 && (rt_uint32_t)data->buf < 0x00080000) /*|| // ITCM
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((rt_uint32_t)data->buf >= 0x20000000 && (rt_uint32_t)data->buf < 0x20080000)*/) // DTCM
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{
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buf = rt_malloc_align(fsl_data.blockSize * fsl_data.blockCount, CACHE_LINESIZE);
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RT_ASSERT(buf != RT_NULL);
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MMCSD_DGB(" malloc buf: %p, data->buf:%p, %d ", buf, data->buf, fsl_data.blockSize * fsl_data.blockCount);
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}
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if ((cmd->cmd_code == WRITE_BLOCK) || (cmd->cmd_code == WRITE_MULTIPLE_BLOCK))
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{
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if (buf)
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{
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MMCSD_DGB(" write(data->buf to buf) ");
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rt_memcpy(buf, data->buf, fsl_data.blockSize * fsl_data.blockCount);
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fsl_data.txData = (uint32_t const *)buf;
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}
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else
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{
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fsl_data.txData = (uint32_t const *)data->buf;
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}
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fsl_data.rxData = NULL;
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}
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else
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{
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if (buf)
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{
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fsl_data.rxData = (uint32_t *)buf;
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}
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else
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{
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fsl_data.rxData = (uint32_t *)data->buf;
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}
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fsl_data.txData = NULL;
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}
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fsl_content.data = &fsl_data;
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}
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else
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{
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fsl_content.data = NULL;
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}
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error = USDHC_TransferBlocking(mmcsd->usdhc_host.base, &dmaConfig, &fsl_content);
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if (error != kStatus_Success)
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{
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SDMMCHOST_ErrorRecovery(mmcsd->usdhc_host.base);
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MMCSD_DGB(" ***USDHC_TransferBlocking error: %d*** --> \n", error);
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cmd->err = -RT_ERROR;
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}
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if (buf)
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{
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if (fsl_data.rxData)
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{
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MMCSD_DGB("read copy buf to data->buf ");
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rt_memcpy(data->buf, buf, fsl_data.blockSize * fsl_data.blockCount);
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}
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rt_free_align(buf);
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}
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if ((cmd->flags & RESP_MASK) == RESP_R2)
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{
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cmd->resp[3] = fsl_command.response[0];
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cmd->resp[2] = fsl_command.response[1];
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cmd->resp[1] = fsl_command.response[2];
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cmd->resp[0] = fsl_command.response[3];
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MMCSD_DGB(" resp 0x%08X 0x%08X 0x%08X 0x%08X\n",
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cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3]);
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}
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else
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{
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cmd->resp[0] = fsl_command.response[0];
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MMCSD_DGB(" resp 0x%08X\n", cmd->resp[0]);
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}
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mmcsd_req_complete(host);
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return;
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}
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static void _mmc_set_iocfg(struct rt_mmcsd_host *host, struct rt_mmcsd_io_cfg *io_cfg)
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{
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struct imxrt_mmcsd *mmcsd;
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unsigned int usdhc_clk;
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unsigned int bus_width;
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uint32_t src_clk;
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RT_ASSERT(host != RT_NULL);
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RT_ASSERT(host->private_data != RT_NULL);
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RT_ASSERT(io_cfg != RT_NULL);
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mmcsd = (struct imxrt_mmcsd *)host->private_data;
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usdhc_clk = io_cfg->clock;
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bus_width = io_cfg->bus_width;
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if (usdhc_clk > IMXRT_MAX_FREQ)
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usdhc_clk = IMXRT_MAX_FREQ;
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#ifdef SOC_IMXRT1170_SERIES
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clock_root_config_t rootCfg = {0};
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/* SYS PLL2 528MHz. */
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const clock_sys_pll2_config_t sysPll2Config = {
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.ssEnable = false,
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};
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CLOCK_InitSysPll2(&sysPll2Config);
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CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd2, 24);
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rootCfg.mux = 4;
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rootCfg.div = 2;
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CLOCK_SetRootClock(kCLOCK_Root_Usdhc1, &rootCfg);
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src_clk = CLOCK_GetRootClockFreq(kCLOCK_Root_Usdhc1);
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#elif defined(SOC_MIMXRT1062DVL6A)
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CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN);
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/*configure system pll PFD0 fractional divider to 24, output clock is 528MHZ * 18 / 24 = 396 MHZ*/
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CLOCK_InitSysPfd(kCLOCK_Pfd0, 24U);
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/* Configure USDHC clock source and divider */
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CLOCK_SetDiv(kCLOCK_Usdhc1Div, 1U); /* USDHC clock root frequency maximum: 198MHZ */
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CLOCK_SetMux(kCLOCK_Usdhc1Mux, 1U);
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src_clk = 396000000U / 2U;
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#else
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src_clk = (CLOCK_GetSysPfdFreq(kCLOCK_Pfd2) / (CLOCK_GetDiv(mmcsd->usdhc_div) + 1U));
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#endif
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MMCSD_DGB("\tsrc_clk: %d, usdhc_clk: %d, bus_width: %d\n", src_clk, usdhc_clk, bus_width);
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if (usdhc_clk)
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{
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USDHC_SetSdClock(mmcsd->usdhc_host.base, src_clk, usdhc_clk);
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/* Change bus width */
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if (bus_width == MMCSD_BUS_WIDTH_8)
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USDHC_SetDataBusWidth(mmcsd->usdhc_host.base, kUSDHC_DataBusWidth8Bit);
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else if (bus_width == MMCSD_BUS_WIDTH_4)
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USDHC_SetDataBusWidth(mmcsd->usdhc_host.base, kUSDHC_DataBusWidth4Bit);
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else if (bus_width == MMCSD_BUS_WIDTH_1)
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USDHC_SetDataBusWidth(mmcsd->usdhc_host.base, kUSDHC_DataBusWidth1Bit);
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else
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RT_ASSERT(RT_NULL);
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}
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}
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#ifdef DEBUG
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static void log_toggle(int en)
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{
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enable_log = en;
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}
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FINSH_FUNCTION_EXPORT(log_toggle, toglle log dumple);
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#endif
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static const struct rt_mmcsd_host_ops ops =
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{
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_mmc_request,
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_mmc_set_iocfg,
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RT_NULL,//_mmc_get_card_status,
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RT_NULL,//_mmc_enable_sdio_irq,
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};
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rt_int32_t _imxrt_mci_init(void)
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{
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struct rt_mmcsd_host *host;
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struct imxrt_mmcsd *mmcsd;
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#if (defined(FSL_FEATURE_USDHC_HAS_HS400_MODE) && (FSL_FEATURE_USDHC_HAS_HS400_MODE))
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uint32_t hs400Capability = 0U;
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#endif
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host = mmcsd_alloc_host();
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if (!host)
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{
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return -RT_ERROR;
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}
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mmcsd = rt_malloc(sizeof(struct imxrt_mmcsd));
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if (!mmcsd)
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{
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rt_kprintf("alloc mci failed\n");
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goto err;
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}
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rt_memset(mmcsd, 0, sizeof(struct imxrt_mmcsd));
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mmcsd->usdhc_host.base = USDHC1;
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//#ifndef SOC_IMXRT1170_SERIES
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// mmcsd->usdhc_div = kCLOCK_Usdhc1Div;
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//#endif
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mmcsd->usdhc_adma2_table = g_usdhcAdma2Table;
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host->ops = &ops;
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host->freq_min = 375000;
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host->freq_max = 25000000;
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host->valid_ocr = VDD_32_33 | VDD_33_34;
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host->flags = MMCSD_BUSWIDTH_4 | MMCSD_MUTBLKWRITE | \
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MMCSD_SUP_HIGHSPEED | MMCSD_SUP_SDIO_IRQ;
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#if defined(FSL_FEATURE_USDHC_INSTANCE_SUPPORT_HS400_MODEn) && (FSL_FEATURE_USDHC_INSTANCE_SUPPORT_HS400_MODEn)
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hs400Capability = (uint32_t)FSL_FEATURE_USDHC_INSTANCE_SUPPORT_HS400_MODEn(mmcsd->usdhc_host.base);
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#endif
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#if (defined(FSL_FEATURE_USDHC_HAS_HS400_MODE) && (FSL_FEATURE_USDHC_HAS_HS400_MODE))
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if (hs400Capability != 0U)
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{
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host->flags |= (uint32_t)MMCSD_SUP_HIGHSPEED_HS400;
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}
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#endif
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host->max_seg_size = 65535;
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host->max_dma_segs = 2;
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//#ifdef SOC_IMXRT1170_SERIES
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host->max_blk_size = SDMMCHOST_SUPPORT_MAX_BLOCK_LENGTH;
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host->max_blk_count = SDMMCHOST_SUPPORT_MAX_BLOCK_COUNT;
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//#else
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// host->max_blk_size = 512;
|
|
// host->max_blk_count = 4096;
|
|
//#endif
|
|
mmcsd->host = host;
|
|
|
|
#ifndef CODE_STORED_ON_SDCARD
|
|
_mmcsd_clk_init(mmcsd);
|
|
_mmcsd_isr_init(mmcsd);
|
|
_mmcsd_gpio_init(mmcsd);
|
|
_mmcsd_host_init(mmcsd);
|
|
#endif
|
|
|
|
host->private_data = mmcsd;
|
|
|
|
mmcsd_change(host);
|
|
|
|
return 0;
|
|
|
|
err:
|
|
mmcsd_free_host(host);
|
|
|
|
return -RT_ENOMEM;
|
|
}
|
|
|
|
int imxrt_mci_init(void)
|
|
{
|
|
/* initilize sd card */
|
|
_imxrt_mci_init();
|
|
|
|
return 0;
|
|
}
|
|
INIT_DEVICE_EXPORT(imxrt_mci_init);
|