157 lines
5.3 KiB
C
157 lines
5.3 KiB
C
/*
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* @brief LPC8xx INPUT MUX chip driver
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*
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* @note
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* Copyright(C) NXP Semiconductors, 2013
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* All rights reserved.
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*
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* @par
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* Software that is described herein is for illustrative purposes only
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* which provides customers with programming information regarding the
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* LPC products. This software is supplied "AS IS" without any warranties of
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* any kind, and NXP Semiconductors and its licensor disclaim any and
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* all warranties, express or implied, including all implied warranties of
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* merchantability, fitness for a particular purpose and non-infringement of
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* intellectual property rights. NXP Semiconductors assumes no responsibility
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* or liability for the use of the software, conveys no license or rights under any
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* patent, copyright, mask work right, or any other intellectual property rights in
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* or to any products. NXP Semiconductors reserves the right to make changes
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* in the software without notification. NXP Semiconductors also makes no
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* representation or warranty that such application will be suitable for the
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* specified use without further testing or modification.
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*
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* @par
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* Permission to use, copy, modify, and distribute this software and its
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* documentation is hereby granted, under NXP Semiconductors' and its
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* licensor's relevant copyrights in the software, without fee, provided that it
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* is used in conjunction with NXP Semiconductors microcontrollers. This
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* copyright, permission, and disclaimer notice must appear in all copies of
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* this code.
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*/
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#ifndef __INMUX_8XX_H_
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#define __INMUX_8XX_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** @defgroup INMUX_8XX CHIP: LPC8xx INPUT Mux Controller driver
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* @ingroup CHIP_8XX_Drivers
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* @{
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*/
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typedef struct {
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__IO uint32_t DMA_INMUX_INMUX[2]; /*!< DMA Trigger Input 20 & 21 PINMUX 0-1 */
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__O uint32_t RESERVED[6]; /*!< Reserved; Should not be used */
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__IO uint32_t SCT0_INMUX[4]; /*!< Input mux register for SCT0; INPUT0-3 */
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} LPC_INMUX_T;
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/**
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* @brief DMA INPUT MUX Index see Chip_INMUX_SetDMAOTrig()
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*/
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typedef enum {
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DMA_INMUX_0, /*!< MUX for DMA input trigger 20 */
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DMA_INMUX_1, /*!< MUX for DMA input trigger 21 */
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}DMA_INMUX_T;
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/**
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* @brief SCT Input Mux Index; See Chip_INMUX_SetSCTInMux()
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*/
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typedef enum {
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SCT_INMUX_0, /*!< Input mux for SCT0; INPUT 0 */
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SCT_INMUX_1, /*!< Input mux for SCT0; INPUT 1 */
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SCT_INMUX_2, /*!< Input mux for SCT0; INPUT 2 */
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SCT_INMUX_3, /*!< Input mux for SCT0; INPUT 3 */
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} SCT_INMUX_T;
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/**
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* @brief SCT INPUT triggers
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*/
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typedef enum {
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SCT_INP_IN0, /*!< SCT0_IN0 selected by Pin Matrix */ /* FIXME: UM hints about changes */
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SCT_INP_IN1, /*!< SCT0_IN1 selected by Pin Matrix */
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SCT_INP_IN2, /*!< SCT0_IN2 selected by Pin Matrix */
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SCT_INP_IN3, /*!< SCT0_IN3 selected by Pin Matrix */
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SCT_INP_ADC_THCMP_IRQ, /*!< ADC Threshold compare IRQ */
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SCT_INP_ACMP_O, /*!< Analog comparator output */
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SCT_INP_ARM_TXEV, /*!< ARM TX Event */
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SCT_INP_DEBUG_HALTED, /*!< Debug halted event */
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} SCT_INP_T;
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/**
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* @brief Select a trigger source for a DMA channel
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* @param pINMUX : The base of INPUT MUX register block
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* @param imux : Index of DMA input mux
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* @param ch : DMA channel ID
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* @return Nothing
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*/
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STATIC INLINE void Chip_INMUX_SetDMAOTrig(LPC_INMUX_T *pINMUX, DMA_INMUX_T imux, DMA_CHID_T ch)
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{
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pINMUX->DMA_INMUX_INMUX[imux] = ch;
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}
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/**
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* @brief Select a trigger source SCT module
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* @param pINMUX : The base of INPUT MUX register block
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* @param isct : Index of SCT input mux
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* @param trig : SCT Input function that will cause the trigger
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* @return Nothing
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*/
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STATIC INLINE void Chip_INMUX_SetSCTInMux(LPC_INMUX_T *pINMUX, SCT_INMUX_T isct, SCT_INP_T trig)
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{
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pINMUX->SCT0_INMUX[isct] = trig;
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}
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/** @defgroup DMATRIGMUX_8XX CHIP: LPC8xx DMA trigger selection driver
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* @{
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*/
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/**
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* @brief DMA trigger pin muxing structure
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*/
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typedef struct { /*!< DMA trigger pin muxing register structure */
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__IO uint32_t DMA_ITRIG_INMUX[MAX_DMA_CHANNEL]; /*!< Trigger input select register for DMA channels */
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} LPC_DMATRIGMUX_T;
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/* DMA triggers that can mapped to DMA channels */
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typedef enum {
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DMATRIG_ADC_SEQA_IRQ = 0, /*!< ADC0 sequencer A interrupt as trigger */
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DMATRIG_ADC_SEQB_IRQ, /*!< ADC0 sequencer B interrupt as trigger */
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DMATRIG_SCT0_DMA0, /*!< SCT 0, DMA 0 as trigger */
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DMATRIG_SCT0_DMA1, /*!< SCT 1, DMA 1 as trigger */
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DMATRIG_ACMP_O, /*!< Analog comparator output */
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DMATRIG_PINT0, /*!< Pin interrupt 0 as trigger */
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DMATRIG_PINT1, /*!< Pin interrupt 1 as trigger */
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DMATRIG_DMA_INMUX0, /*!< DMA Trigger MUX0 */
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DMATRIG_DMA_INMUX1, /*!< DMA Trigger MUX1 */
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} DMA_TRIGSRC_T;
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/**
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* @brief Select a trigger source for a DMA channel
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* @param pDMATRIG : The base of DMA trigger setup block on the chip
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* @param ch : DMA channel ID
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* @param trig : Trigger source for the DMA channel
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* @return Nothing
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* @note A DMA trigger source only needs to be setup when the DMA is setup
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* for hardware trigger mode (when Chip_DMA_SetupChannelConfig() is
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* called with DMA_CFG_HWTRIGEN as OR'ed option).
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*/
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STATIC INLINE void Chip_DMATRIGMUX_SetInputTrig(LPC_DMATRIGMUX_T *pDMATRIG, DMA_CHID_T ch, DMA_TRIGSRC_T trig)
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{
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pDMATRIG->DMA_ITRIG_INMUX[ch] = (uint32_t) trig;
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}
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/**
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* @}
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*/
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/**
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* @}
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*/
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#ifdef __cplusplus
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}
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#endif
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#endif /* __INMUX_8XX_H_ */
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