130 lines
3.7 KiB
C
130 lines
3.7 KiB
C
/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2020-04-16 bigmagic first version
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*/
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#include <rthw.h>
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#include <rtthread.h>
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#include "board.h"
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#include "drv_uart.h"
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#include "cp15.h"
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#include "mmu.h"
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#include "mbox.h"
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#ifdef BSP_USING_CORETIMER
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static rt_uint64_t timerStep;
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int rt_hw_get_gtimer_frq(void);
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void rt_hw_set_gtimer_val(rt_uint64_t value);
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int rt_hw_get_gtimer_val(void);
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int rt_hw_get_cntpct_val(void);
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void rt_hw_gtimer_enable(void);
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void core0_timer_enable_interrupt_controller(void)
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{
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CORE0_TIMER_IRQ_CTRL |= NON_SECURE_TIMER_IRQ;
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}
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#endif
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void rt_hw_timer_isr(int vector, void *parameter)
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{
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#ifdef BSP_USING_CORETIMER
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rt_hw_set_gtimer_val(timerStep);
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#else
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ARM_TIMER_IRQCLR = 0;
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#endif
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rt_tick_increase();
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}
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void rt_hw_timer_init(void)
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{
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#ifdef BSP_USING_CORETIMER
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rt_hw_interrupt_install(TIMER_IRQ, rt_hw_timer_isr, RT_NULL, "tick");
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rt_hw_interrupt_umask(TIMER_IRQ);
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__ISB();
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timerStep = rt_hw_get_gtimer_frq();
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__DSB();
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timerStep /= RT_TICK_PER_SECOND;
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rt_hw_gtimer_enable();
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rt_hw_set_gtimer_val(timerStep);
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core0_timer_enable_interrupt_controller();
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#else
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rt_uint32_t apb_clock = 0;
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rt_uint32_t timer_clock = 1000000;
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apb_clock = bcm271x_mbox_clock_get_rate(CORE_CLK_ID);
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ARM_TIMER_PREDIV = (apb_clock/timer_clock - 1);
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ARM_TIMER_RELOAD = 0;
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ARM_TIMER_LOAD = 0;
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ARM_TIMER_IRQCLR = 0;
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ARM_TIMER_CTRL = 0;
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ARM_TIMER_RELOAD = 1000000 / RT_TICK_PER_SECOND;
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ARM_TIMER_LOAD = 1000000 / RT_TICK_PER_SECOND;
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/* 23-bit counter, enable interrupt, enable timer */
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ARM_TIMER_CTRL = (1 << 1) | (1 << 5) | (1 << 7);
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rt_hw_interrupt_install(ARM_TIMER_IRQ, rt_hw_timer_isr, RT_NULL, "tick");
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rt_hw_interrupt_umask(ARM_TIMER_IRQ);
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#endif
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}
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void idle_wfi(void)
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{
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asm volatile ("wfi");
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}
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/**
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* Initialize the Hardware related stuffs. Called from rtthread_startup()
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* after interrupt disabled.
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*/
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void rt_hw_board_init(void)
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{
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mmu_init();
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armv8_map(0, 0, 0x6400000, MEM_ATTR_MEMORY);
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armv8_map(0xFE200000, 0xFE200000, 0x200000, MEM_ATTR_IO);//uart gpio
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armv8_map(0xFF800000, 0xFF800000, 0x200000, MEM_ATTR_IO);//gic timer
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armv8_map(ARM_TIMER_BASE, ARM_TIMER_BASE, 0x200000, MEM_ATTR_IO);//arm timer
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armv8_map(STIMER_BASE, STIMER_BASE, 0x200000, MEM_ATTR_IO);//stimer
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armv8_map(MMC2_BASE_ADDR, MMC2_BASE_ADDR, 0x200000, MEM_ATTR_IO);//mmc
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armv8_map(MBOX_ADDR, MBOX_ADDR, 0x200000, MEM_ATTR_IO);//mbox msg
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armv8_map((unsigned long)MAC_REG_BASE_ADDR, (unsigned long)MAC_REG_BASE_ADDR, 0x80000, MEM_ATTR_IO);//mac
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armv8_map(SEND_DATA_NO_CACHE, SEND_DATA_NO_CACHE, 0x200000, MEM_ATTR_MEMORY);//eth send
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armv8_map(RECV_DATA_NO_CACHE, RECV_DATA_NO_CACHE, 0x200000, MEM_ATTR_MEMORY);//eth recv
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mmu_enable();
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/* initialize hardware interrupt */
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rt_hw_interrupt_init(); // in libcpu/interrupt.c. Set some data structures, no operation on device
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rt_hw_vector_init(); // in libcpu/interrupt.c. == rt_cpu_vector_set_base((rt_ubase_t)&system_vectors);
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/* initialize uart */
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rt_hw_uart_init(); // driver/drv_uart.c
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#ifdef RT_USING_CONSOLE
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/* set console device */
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rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
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#endif /* RT_USING_CONSOLE */
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#ifdef RT_USING_HEAP
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/* initialize memory system */
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rt_kprintf("heap: 0x%08x - 0x%08x\n", RT_HW_HEAP_BEGIN, RT_HW_HEAP_END);
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rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END);
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#endif
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/* initialize timer for os tick */
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rt_hw_timer_init();
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rt_thread_idle_sethook(idle_wfi);
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#ifdef RT_USING_COMPONENTS_INIT
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rt_components_board_init();
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#endif
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}
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