195 lines
5.8 KiB
C
195 lines
5.8 KiB
C
/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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*/
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#ifndef _DMA_H
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#define _DMA_H
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#define MAX_DMA_CHANNELS 8
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/* 8237 DMA controllers */
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#define IO_DMA1_BASE 0x00 /* 8 bit slave DMA, channels 0..3 */
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#define IO_DMA2_BASE 0xC0 /* 16 bit master DMA, ch 4(=slave input)..7 */
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/* DMA controller registers */
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#define DMA1_CMD_REG 0x08 /* command register (w) */
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#define DMA1_STAT_REG 0x08 /* status register (r) */
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#define DMA1_REQ_REG 0x09 /* request register (w) */
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#define DMA1_MASK_REG 0x0A /* single-channel mask (w) */
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#define DMA1_MODE_REG 0x0B /* mode register (w) */
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#define DMA1_CLEAR_FF_REG 0x0C /* clear pointer flip-flop (w) */
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#define DMA1_TEMP_REG 0x0D /* Temporary Register (r) */
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#define DMA1_RESET_REG 0x0D /* Master Clear (w) */
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#define DMA1_CLR_MASK_REG 0x0E /* Clear Mask */
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#define DMA1_MASK_ALL_REG 0x0F /* all-channels mask (w) */
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#define DMA2_CMD_REG 0xD0 /* command register (w) */
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#define DMA2_STAT_REG 0xD0 /* status register (r) */
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#define DMA2_REQ_REG 0xD2 /* request register (w) */
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#define DMA2_MASK_REG 0xD4 /* single-channel mask (w) */
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#define DMA2_MODE_REG 0xD6 /* mode register (w) */
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#define DMA2_CLEAR_FF_REG 0xD8 /* clear pointer flip-flop (w) */
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#define DMA2_TEMP_REG 0xDA /* Temporary Register (r) */
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#define DMA2_RESET_REG 0xDA /* Master Clear (w) */
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#define DMA2_CLR_MASK_REG 0xDC /* Clear Mask */
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#define DMA2_MASK_ALL_REG 0xDE /* all-channels mask (w) */
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#define DMA_ADDR_0 0x00 /* DMA address registers */
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#define DMA_ADDR_1 0x02
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#define DMA_ADDR_2 0x04
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#define DMA_ADDR_3 0x06
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#define DMA_ADDR_4 0xC0
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#define DMA_ADDR_5 0xC4
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#define DMA_ADDR_6 0xC8
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#define DMA_ADDR_7 0xCC
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#define DMA_CNT_0 0x01 /* DMA count registers */
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#define DMA_CNT_1 0x03
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#define DMA_CNT_2 0x05
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#define DMA_CNT_3 0x07
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#define DMA_CNT_4 0xC2
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#define DMA_CNT_5 0xC6
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#define DMA_CNT_6 0xCA
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#define DMA_CNT_7 0xCE
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#define DMA_PAGE_0 0x87 /* DMA page registers */
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#define DMA_PAGE_1 0x83
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#define DMA_PAGE_2 0x81
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#define DMA_PAGE_3 0x82
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#define DMA_PAGE_5 0x8B
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#define DMA_PAGE_6 0x89
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#define DMA_PAGE_7 0x8A
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#define DMA_MODE_READ 0x44 /* I/O to memory, no autoinit, increment, single mode */
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#define DMA_MODE_WRITE 0x48 /* memory to I/O, no autoinit, increment, single mode */
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#define DMA_MODE_CASCADE 0xC0 /* pass thru DREQ->HRQ, DACK<-HLDA only */
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/*
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* 启用指定的DMA通道
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*/
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static __inline__ void EnableDma(unsigned int dmanr)
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{
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if (dmanr<=3)
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OUTB(dmanr, DMA1_MASK_REG);
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else
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OUTB(dmanr & 3, DMA2_MASK_REG);
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}
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/*
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* 禁用指定的DMA通道
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*/
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static __inline__ void DisableDma(unsigned int dmanr)
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{
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if (dmanr<=3)
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OUTB(dmanr | 4, DMA1_MASK_REG);
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else
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OUTB((dmanr & 3) | 4, DMA2_MASK_REG);
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}
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/*
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* 清空DMA 晶体计数器
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*/
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static __inline__ void ClearDmaFF(unsigned int dmanr)
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{
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if (dmanr<=3)
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OUTB(0, DMA1_CLEAR_FF_REG);
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else
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OUTB(0, DMA2_CLEAR_FF_REG);
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}
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/*
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* 清空DMA 晶体计数器
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*/
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static __inline__ void SetDmaMode(unsigned int dmanr, char mode)
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{
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if (dmanr<=3)
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OUTB(mode | dmanr, DMA1_MODE_REG);
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else
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OUTB(mode | (dmanr&3), DMA2_MODE_REG);
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}
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/*
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* 设定DMA 页面寄存器
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*/
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static __inline__ void SetDmaPage(unsigned int dmanr, char pagenr)
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{
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switch(dmanr) {
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case 0:
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OUTB(pagenr, DMA_PAGE_0);
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break;
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case 1:
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OUTB(pagenr, DMA_PAGE_1);
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break;
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case 2:
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OUTB(pagenr, DMA_PAGE_2);
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break;
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case 3:
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OUTB(pagenr, DMA_PAGE_3);
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break;
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case 5:
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OUTB(pagenr & 0xfe, DMA_PAGE_5);
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break;
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case 6:
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OUTB(pagenr & 0xfe, DMA_PAGE_6);
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break;
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case 7:
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OUTB(pagenr & 0xfe, DMA_PAGE_7);
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break;
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}
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}
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/*
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* 设定DMA 传输高速缓冲区地址
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*/
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static __inline__ void SetDmaAddr(unsigned int dmanr, unsigned int a)
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{
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SetDmaPage(dmanr, a>>16);
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if (dmanr <= 3) {
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OUTB( a & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE );
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OUTB( (a>>8) & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE );
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} else {
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OUTB( (a>>1) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
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OUTB( (a>>9) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
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}
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}
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/*
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* 设定DMA 传输块数
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*/
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static __inline__ void SetDmaCount(unsigned int dmanr, unsigned int count)
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{
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count--;
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if (dmanr <= 3) {
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OUTB( count & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE );
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OUTB( (count>>8) & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE );
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} else {
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OUTB( (count>>1) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
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OUTB( (count>>9) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
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}
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}
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/*
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* 获得DMA 传输剩余块数
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*/
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static __inline__ int GetDmaResidue(unsigned int dmanr)
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{
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unsigned int io_port = (dmanr<=3)? ((dmanr&3)<<1) + 1 + IO_DMA1_BASE
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: ((dmanr&3)<<2) + 2 + IO_DMA2_BASE;
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/* using short to get 16-bit wrap around */
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unsigned short count;
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count = 1 + inb(io_port);
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count += inb(io_port) << 8;
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return (dmanr<=3)? count : (count<<1);
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}
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#endif
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