285 lines
7.6 KiB
C
285 lines
7.6 KiB
C
/*
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* Copyright (c) 2006-2023, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2010-01-25 Bernard first version
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* 2012-05-31 aozima Merge all of the C source code into cpuport.c
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* 2012-08-17 aozima fixed bug: store r8 - r11.
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* 2012-12-23 aozima stack addr align to 8byte.
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* 2023-01-22 rose_man add RT_USING_SMP
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*/
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#include <rtthread.h>
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#include <rthw.h>
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#include <rtthread.h>
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#include <stdint.h>
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#include "board.h"
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#ifdef RT_USING_SMP
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#include "hardware/structs/sio.h"
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#include "hardware/irq.h"
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#include "pico/sync.h"
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#include "pico/multicore.h"
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int rt_hw_cpu_id(void)
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{
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return sio_hw->cpuid;
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}
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void rt_hw_spin_lock_init(rt_hw_spinlock_t *lock)
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{
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static uint8_t spin_cnt = 0;
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if ( spin_cnt < 32)
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{
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lock->slock = (rt_uint32_t)spin_lock_instance(spin_cnt);
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spin_cnt = spin_cnt + 1;
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}
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else
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{
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lock->slock = 0;
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}
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}
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void rt_hw_spin_lock(rt_hw_spinlock_t *lock)
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{
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if ( lock->slock != 0 )
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{
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spin_lock_unsafe_blocking((spin_lock_t*)lock->slock);
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}
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}
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void rt_hw_spin_unlock(rt_hw_spinlock_t *lock)
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{
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if ( lock->slock != 0 )
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{
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spin_unlock_unsafe((spin_lock_t*)lock->slock);
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}
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}
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void secondary_cpu_c_start(void)
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{
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irq_set_enabled(SIO_IRQ_PROC1,RT_TRUE);
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extern uint32_t systick_config(uint32_t ticks);
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systick_config(frequency_count_khz(CLOCKS_FC0_SRC_VALUE_ROSC_CLKSRC)*10000/RT_TICK_PER_SECOND);
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rt_hw_spin_lock(&_cpus_lock);
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rt_system_scheduler_start();
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}
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void rt_hw_secondary_cpu_up(void)
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{
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multicore_launch_core1(secondary_cpu_c_start);
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irq_set_enabled(SIO_IRQ_PROC0,RT_TRUE);
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}
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void rt_hw_secondary_cpu_idle_exec(void)
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{
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asm volatile ("wfi");
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}
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#define IPI_MAGIC 0x5a5a
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void rt_hw_ipi_send(int ipi_vector, unsigned int cpu_mask)
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{
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sio_hw->fifo_wr = IPI_MAGIC;
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}
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void rt_hw_ipi_handler(void)
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{
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uint32_t status = sio_hw->fifo_st;
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if ( status & (SIO_FIFO_ST_ROE_BITS | SIO_FIFO_ST_WOF_BITS) )
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{
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sio_hw->fifo_st = 0;
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}
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if ( status & SIO_FIFO_ST_VLD_BITS )
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{
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if ( sio_hw->fifo_rd == IPI_MAGIC )
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{
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//rt_schedule();
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}
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}
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}
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void isr_irq15(void)
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{
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rt_hw_ipi_handler();
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}
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void isr_irq16(void)
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{
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rt_hw_ipi_handler();
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}
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struct __rt_thread_switch_array
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{
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rt_ubase_t flag;
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rt_ubase_t from;
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rt_ubase_t to;
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};
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struct __rt_thread_switch_array rt_thread_switch_array[2] = { {0,0,0}, {0,0,0} };
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void __rt_cpu_switch(rt_ubase_t from, rt_ubase_t to, struct rt_thread *thread)
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{
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struct rt_cpu* pcpu = rt_cpu_self();
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rt_uint32_t cpuid = rt_hw_cpu_id();
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if ( rt_thread_switch_array[cpuid].flag != 1)
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{
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rt_thread_switch_array[cpuid].flag = 1;
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rt_thread_switch_array[cpuid].from = from;
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}
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rt_thread_switch_array[cpuid].to = to;
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if ( pcpu->current_thread != RT_NULL )
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{
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thread->cpus_lock_nest = pcpu->current_thread->cpus_lock_nest;
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thread->critical_lock_nest = pcpu->current_thread->critical_lock_nest;
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thread->scheduler_lock_nest = pcpu->current_thread->scheduler_lock_nest;
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}
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pcpu->current_thread = thread;
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if (!thread->cpus_lock_nest)
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{
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rt_hw_spin_unlock(&_cpus_lock);
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}
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}
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#endif /*RT_USING_SMP*/
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struct exception_stack_frame
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{
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rt_uint32_t r0;
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rt_uint32_t r1;
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rt_uint32_t r2;
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rt_uint32_t r3;
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rt_uint32_t r12;
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rt_uint32_t lr;
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rt_uint32_t pc;
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rt_uint32_t psr;
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};
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struct stack_frame
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{
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/* r4 ~ r7 low register */
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rt_uint32_t r4;
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rt_uint32_t r5;
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rt_uint32_t r6;
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rt_uint32_t r7;
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/* r8 ~ r11 high register */
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rt_uint32_t r8;
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rt_uint32_t r9;
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rt_uint32_t r10;
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rt_uint32_t r11;
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struct exception_stack_frame exception_stack_frame;
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};
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/* flag in interrupt handling */
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rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread;
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rt_uint32_t rt_thread_switch_interrupt_flag;
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/**
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* This function will initialize thread stack
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*
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* @param tentry the entry of thread
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* @param parameter the parameter of entry
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* @param stack_addr the beginning stack address
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* @param texit the function will be called when thread exit
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*
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* @return stack address
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*/
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rt_uint8_t *rt_hw_stack_init(void *tentry,
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void *parameter,
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rt_uint8_t *stack_addr,
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void *texit)
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{
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struct stack_frame *stack_frame;
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rt_uint8_t *stk;
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unsigned long i;
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stk = stack_addr + sizeof(rt_uint32_t);
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stk = (rt_uint8_t *)RT_ALIGN_DOWN((rt_uint32_t)stk, 8);
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stk -= sizeof(struct stack_frame);
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stack_frame = (struct stack_frame *)stk;
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/* init all register */
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for (i = 0; i < sizeof(struct stack_frame) / sizeof(rt_uint32_t); i ++)
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{
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((rt_uint32_t *)stack_frame)[i] = 0xdeadbeef;
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}
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stack_frame->exception_stack_frame.r0 = (unsigned long)parameter; /* r0 : argument */
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stack_frame->exception_stack_frame.r1 = 0; /* r1 */
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stack_frame->exception_stack_frame.r2 = 0; /* r2 */
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stack_frame->exception_stack_frame.r3 = 0; /* r3 */
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stack_frame->exception_stack_frame.r12 = 0; /* r12 */
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stack_frame->exception_stack_frame.lr = (unsigned long)texit; /* lr */
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stack_frame->exception_stack_frame.pc = (unsigned long)tentry; /* entry point, pc */
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stack_frame->exception_stack_frame.psr = 0x01000000L; /* PSR */
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/* return task's current stack address */
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return stk;
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}
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#if defined(RT_USING_FINSH) && defined(MSH_USING_BUILT_IN_COMMANDS)
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extern long list_thread(void);
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#endif
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extern rt_thread_t rt_current_thread;
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/**
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* fault exception handling
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*/
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void rt_hw_hard_fault_exception(struct exception_stack_frame *contex)
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{
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rt_kprintf("psr: 0x%08x\n", contex->psr);
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rt_kprintf(" pc: 0x%08x\n", contex->pc);
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rt_kprintf(" lr: 0x%08x\n", contex->lr);
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rt_kprintf("r12: 0x%08x\n", contex->r12);
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rt_kprintf("r03: 0x%08x\n", contex->r3);
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rt_kprintf("r02: 0x%08x\n", contex->r2);
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rt_kprintf("r01: 0x%08x\n", contex->r1);
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rt_kprintf("r00: 0x%08x\n", contex->r0);
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#ifdef RT_USING_SMP
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rt_thread_t rt_current_thread = rt_thread_self();
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rt_kprintf("hard fault on cpu : %d on thread: %s\n", rt_current_thread->oncpu, rt_current_thread->parent.name);
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#else
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rt_kprintf("hard fault on thread: %s\n", rt_current_thread->parent.name);
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#endif
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#if defined(RT_USING_FINSH) && defined(MSH_USING_BUILT_IN_COMMANDS)
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list_thread();
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#endif
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while (1);
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}
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#define SCB_CFSR (*(volatile const unsigned *)0xE000ED28) /* Configurable Fault Status Register */
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#define SCB_HFSR (*(volatile const unsigned *)0xE000ED2C) /* HardFault Status Register */
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#define SCB_MMAR (*(volatile const unsigned *)0xE000ED34) /* MemManage Fault Address register */
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#define SCB_BFAR (*(volatile const unsigned *)0xE000ED38) /* Bus Fault Address Register */
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#define SCB_AIRCR (*(volatile unsigned long *)0xE000ED0C) /* Reset control Address Register */
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#define SCB_RESET_VALUE 0x05FA0004 /* Reset value, write to SCB_AIRCR can reset cpu */
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#define SCB_CFSR_MFSR (*(volatile const unsigned char*)0xE000ED28) /* Memory-management Fault Status Register */
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#define SCB_CFSR_BFSR (*(volatile const unsigned char*)0xE000ED29) /* Bus Fault Status Register */
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#define SCB_CFSR_UFSR (*(volatile const unsigned short*)0xE000ED2A) /* Usage Fault Status Register */
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/**
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* reset CPU
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*/
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void rt_hw_cpu_reset(void)
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{
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SCB_AIRCR = SCB_RESET_VALUE;//((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |SCB_AIRCR_SYSRESETREQ_Msk);
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}
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