349 lines
9.6 KiB
ArmAsm
349 lines
9.6 KiB
ArmAsm
;/*
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; * Copyright (c) 2006-2022, RT-Thread Development Team
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; *
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; * SPDX-License-Identifier: Apache-2.0
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; *
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; * Change Logs:
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; * Date Author Notes
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; * 2024-03-11 Wangyuqiang first version
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; */
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;@-------------------------------------------------------------------------------
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;@ sys_core.asm
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;@
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;@ (c) Texas Instruments 2009-2013, All rights reserved.
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;@
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; Constants
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Mode_USR EQU 0x10
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Mode_FIQ EQU 0x11
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Mode_IRQ EQU 0x12
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Mode_SVC EQU 0x13
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Mode_ABT EQU 0x17
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Mode_UND EQU 0x1B
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Mode_SYS EQU 0x1F
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I_Bit EQU 0x80
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F_Bit EQU 0x40
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UND_Stack_Size EQU 0x00000000
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SVC_Stack_Size EQU 0x00000000
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ABT_Stack_Size EQU 0x00000000
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FIQ_Stack_Size EQU 0x00001000
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IRQ_Stack_Size EQU 0x00001000
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IMPORT entry
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IMPORT rt_hw_trap_svc
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IMPORT rt_hw_trap_pabt
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IMPORT rt_hw_trap_dabt
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IMPORT rt_hw_trap_resv
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IMPORT rt_hw_trap_swi
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IMPORT rt_hw_trap_undef
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IMPORT system_init
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IMPORT __iar_program_start
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; Define sections
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SECTION .text:CODE:REORDER:NOROOT(2)
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; Define stack start and top
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EXPORT stack_start
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EXPORT stack_top
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; Align stack start to a 4-byte boundary (32-bit word)
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ALIGNRAM 5
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stack_start:
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; Reserve stack memory
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REPT (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + FIQ_Stack_Size + IRQ_Stack_Size)
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DCB 0 ; Define a byte of data and clear it to zero
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ENDR
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; Define stack top label
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stack_top:
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; Define code section
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SECTION .text:CODE:REORDER:NOROOT(2)
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; Specify ARM mode
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THUMB
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;@-------------------------------------------------------------------------------
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;@ Enable RAM ECC Support
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EXPORT _coreEnableRamEcc_
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_coreEnableRamEcc_:
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stmfd sp!, {r0}
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mrc p15, #0x00, r0, c1, c0, #0x01
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orr r0, r0, #0x0C000000
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mcr p15, #0x00, r0, c1, c0, #0x01
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ldmfd sp!, {r0}
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bx lr
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;@-------------------------------------------------------------------------------
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;@ Disable RAM ECC Support
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EXPORT _coreDisableRamEcc_
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_coreDisableRamEcc_:
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stmfd sp!, {r0}
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mrc p15, #0x00, r0, c1, c0, #0x01
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bic r0, r0, #0x0C000000
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mcr p15, #0x00, r0, c1, c0, #0x01
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ldmfd sp!, {r0}
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bx lr
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;@-------------------------------------------------------------------------------
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;@ Enable Flash ECC Support
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EXPORT _coreEnableFlashEcc_
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_coreEnableFlashEcc_:
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stmfd sp!, {r0}
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mrc p15, #0x00, r0, c1, c0, #0x01
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orr r0, r0, #0x02000000
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dmb
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mcr p15, #0x00, r0, c1, c0, #0x01
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ldmfd sp!, {r0}
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bx lr
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;@-------------------------------------------------------------------------------
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;@ Disable Flash ECC Support
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EXPORT _coreDisableFlashEcc_
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_coreDisableFlashEcc_:
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stmfd sp!, {r0}
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mrc p15, #0x00, r0, c1, c0, #0x01
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bic r0, r0, #0x02000000
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mcr p15, #0x00, r0, c1, c0, #0x01
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ldmfd sp!, {r0}
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bx lr
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;@-------------------------------------------------------------------------------
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;@ Get data fault status register
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EXPORT _coreGetDataFault_
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_coreGetDataFault_:
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mrc p15, #0, r0, c5, c0, #0
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bx lr
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;@-------------------------------------------------------------------------------
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;@ Clear data fault status register
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EXPORT _coreClearDataFault_
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_coreClearDataFault_:
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stmfd sp!, {r0}
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mov r0, #0
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mcr p15, #0, r0, c5, c0, #0
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ldmfd sp!, {r0}
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bx lr
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;@-------------------------------------------------------------------------------
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;@ Get instruction fault status register
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EXPORT _coreGetInstructionFault_
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_coreGetInstructionFault_:
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mrc p15, #0, r0, c5, c0, #1
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bx lr
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;@-------------------------------------------------------------------------------
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;@ Clear instruction fault status register
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EXPORT _coreClearInstructionFault_
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_coreClearInstructionFault_:
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stmfd sp!, {r0}
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mov r0, #0
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mcr p15, #0, r0, c5, c0, #1
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ldmfd sp!, {r0}
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bx lr
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;@-------------------------------------------------------------------------------
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;@ Get data fault address register
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EXPORT _coreGetDataFaultAddress_
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_coreGetDataFaultAddress_:
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mrc p15, #0, r0, c6, c0, #0
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bx lr
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;@-------------------------------------------------------------------------------
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;@ Clear data fault address register
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EXPORT _coreClearDataFaultAddress_
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_coreClearDataFaultAddress_:
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stmfd sp!, {r0}
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mov r0, #0
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mcr p15, #0, r0, c6, c0, #0
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ldmfd sp!, {r0}
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bx lr
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;@-------------------------------------------------------------------------------
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;@ Get instruction fault address register
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EXPORT _coreGetInstructionFaultAddress_
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_coreGetInstructionFaultAddress_:
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mrc p15, #0, r0, c6, c0, #2
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bx lr
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;@-------------------------------------------------------------------------------
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;@ Clear instruction fault address register
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EXPORT _coreClearInstructionFaultAddress_
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_coreClearInstructionFaultAddress_:
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stmfd sp!, {r0}
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mov r0, #0
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mcr p15, #0, r0, c6, c0, #2
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ldmfd sp!, {r0}
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bx lr
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;@-------------------------------------------------------------------------------
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;@ Get auxiliary data fault status register
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EXPORT _coreGetAuxiliaryDataFault_
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_coreGetAuxiliaryDataFault_:
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mrc p15, #0, r0, c5, c1, #0
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bx lr
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;@-------------------------------------------------------------------------------
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;@ Clear auxiliary data fault status register
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EXPORT _coreClearAuxiliaryDataFault_
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_coreClearAuxiliaryDataFault_:
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stmfd sp!, {r0}
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mov r0, #0
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mcr p15, #0, r0, c5, c1, #0
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ldmfd sp!, {r0}
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bx lr
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;@-------------------------------------------------------------------------------
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;@ Get auxiliary instruction fault status register
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EXPORT _coreGetAuxiliaryInstructionFault_
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_coreGetAuxiliaryInstructionFault_:
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mrc p15, #0, r0, c5, c1, #1
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bx lr
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;@-------------------------------------------------------------------------------
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;@ Clear auxiliary instruction fault status register
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EXPORT _coreClearAuxiliaryInstructionFault_
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_coreClearAuxiliaryInstructionFault_:
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stmfd sp!, {r0}
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mov r0, #0
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mrc p15, #0, r0, c5, c1, #1
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ldmfd sp!, {r0}
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bx lr
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;@-------------------------------------------------------------------------------
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;@ Work Around for Errata CORTEX-R4#57:
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;@
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;@ Errata Description:
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;@ Conditional VMRS APSR_Nzcv, FPSCR May Evaluate With Incorrect Flags
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;@ Workaround:
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;@ Disable out-of-order single-precision floating point
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;@ multiply-accumulate instruction completion
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EXPORT _errata_CORTEXR4_57_
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_errata_CORTEXR4_57_:
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push {r0}
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mrc p15, #0, r0, c15, c0, #0 ;@ Read Secondary Auxiliary Control Register
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orr r0, r0, #0x10000 ;@ Set BIT 16 (Set DOOFMACS)
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mcr p15, #0, r0, c15, c0, #0 ;@ Write Secondary Auxiliary Control Register
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pop {r0}
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bx lr
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;@-------------------------------------------------------------------------------
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;@ Work Around for Errata CORTEX-R4#66:
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;@
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;@ Errata Description:
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;@ Register Corruption During A Load-Multiple Instruction At
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;@ an Exception Vector
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;@ Workaround:
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;@ Disable out-of-order completion for divide instructions in
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;@ Auxiliary Control register
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EXPORT _errata_CORTEXR4_66_
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_errata_CORTEXR4_66_:
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push {r0}
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mrc p15, #0, r0, c1, c0, #1 ;@ Read Auxiliary Control register
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orr r0, r0, #0x80 ;@ Set BIT 7 (Disable out-of-order completion
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;@ for divide instructions.)
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mcr p15, #0, r0, c1, c0, #1 ;@ Write Auxiliary Control register
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pop {r0}
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bx lr
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EXPORT turnon_VFP
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turnon_VFP:
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;@ Enable FPV
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stmdb sp!, {r0}
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fmrx r0, fpexc
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orr r0, r0, #0x40000000
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fmxr fpexc, r0
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ldmia sp!, {r0}
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subs pc, lr, #4
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macro push_svc_reg
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sub sp, sp, #17 * 4 ;@/* Sizeof(struct rt_hw_exp_stack) */
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stmia sp, {r0 - r12} ;@/* Calling r0-r12 */
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mov r0, sp
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mrs r6, spsr ;@/* Save CPSR */
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str lr, [r0, #15*4] ;@/* Push PC */
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str r6, [r0, #16*4] ;@/* Push CPSR */
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cps #Mode_SVC
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str sp, [r0, #13*4] ;@/* Save calling SP */
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str lr, [r0, #14*4] ;@/* Save calling PC */
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endm
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EXPORT SWI_Handler
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SWI_Handler:
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push_svc_reg
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bl rt_hw_trap_swi
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b .
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EXPORT Undefined_Handler
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Undefined_Handler:
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push_svc_reg
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bl rt_hw_trap_undef
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b .
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EXPORT SVC_Handler
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SVC_Handler:
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push_svc_reg
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bl rt_hw_trap_svc
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b .
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EXPORT Prefetch_Handler
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Prefetch_Handler:
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push_svc_reg
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bl rt_hw_trap_pabt
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b .
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EXPORT Abort_Handler
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Abort_Handler:
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push_svc_reg
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bl rt_hw_trap_dabt
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b .
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EXPORT Reserved_Handler
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Reserved_Handler:
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push_svc_reg
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bl rt_hw_trap_resv
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b .
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END
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