90 lines
3.1 KiB
C
90 lines
3.1 KiB
C
/*
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* Change Logs:
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* Date Author Notes
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* 2021-04-20 liuhy the first version
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*
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* Copyright (C) 2021 Shanghai Eastsoft Microelectronics Co., Ltd. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the License); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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*/
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#ifndef __ES_CONF_INFO_CMU_H__
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#define __ES_CONF_INFO_CMU_H__
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#include <ald_cmu.h>
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/* 时钟树 配置 */
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#define ES_C_MUL_9 CMU_PLL1_OUTPUT_36M
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#define ES_C_MUL_12 CMU_PLL1_OUTPUT_48M
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#define ES_C_MUL_18 CMU_PLL1_OUTPUT_72M
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#define ES_C_MUL_24 CMU_PLL1_OUTPUT_96M
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#define ES_C_DIV_1 CMU_DIV_1
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#define ES_C_DIV_2 CMU_DIV_2
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#define ES_C_DIV_4 CMU_DIV_4
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#define ES_C_DIV_8 CMU_DIV_8
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#define ES_C_DIV_16 CMU_DIV_16
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#define ES_C_DIV_32 CMU_DIV_32
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#define ES_C_DIV_64 CMU_DIV_64
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#define ES_C_DIV_128 CMU_DIV_128
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#define ES_C_DIV_256 CMU_DIV_256
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#define ES_C_DIV_512 CMU_DIV_512
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#define ES_C_DIV_1024 CMU_DIV_1024
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#define ES_C_DIV_2048 CMU_DIV_2048
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#define ES_C_DIV_4096 CMU_DIV_4096
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#define ES_C_HOSC_DIV_1 CMU_PLL1_INPUT_HOSC
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#define ES_C_HOSC_DIV_2 CMU_PLL1_INPUT_HOSC_2
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#define ES_C_HOSC_DIV_3 CMU_PLL1_INPUT_HOSC_3
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#define ES_C_HOSC_DIV_4 CMU_PLL1_INPUT_HOSC_4
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#define ES_C_HOSC_DIV_5 CMU_PLL1_INPUT_HOSC_5
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#define ES_C_HOSC_DIV_6 CMU_PLL1_INPUT_HOSC_6
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#define ES_C_HRC_DIV_6 CMU_PLL1_INPUT_HRC_6
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#define ES_PLL1_REFER_CLK ES_C_HOSC_DIV_3
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#define ES_PLL1_OUT_CLK ES_C_MUL_18
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#define ES_CMU_PLL1_EN ES_C_ENABLE
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#define ES_CMU_PLL1_SAFE_EN ES_C_DISABLE
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#define ES_CMU_LOSC_EN ES_C_ENABLE
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#define ES_CMU_LRC_EN ES_C_ENABLE
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#define ES_CMU_HOSC_EN ES_C_ENABLE
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#define ES_CMU_HRC_EN ES_C_ENABLE
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#define ES_CMU_SYS_DIV ES_C_DIV_1
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#define ES_CMU_HCLK_1_DIV ES_C_DIV_2
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#define ES_CMU_HCLK_2_DIV ES_C_DIV_2
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#define ES_CMU_PCLK_1_DIV ES_C_DIV_2
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#define ES_CMU_PCLK_2_DIV ES_C_DIV_4
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#define ES_SYS_CLK_SOURSE CMU_CLOCK_PLL1
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#define ES_PLL_CLK 72000000
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#define ES_SYS_SOURCE_CLK 72000000
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#define ES_SYS_CLK 72000000
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#define ES_PCLK1_CLK 36000000
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#define ES_PCLK2_CLK 18000000
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#define ES_HCLK1_CLK 36000000
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#define ES_HCLK2_CLK 36000000
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#define ES_CMU_EXTERN_CLK_LOSC 32768
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#define ES_CMU_EXTERN_CLK_HOSC 12000000
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#endif
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