252 lines
7.5 KiB
C
252 lines
7.5 KiB
C
/*
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* Copyright 2017-2020 NXP
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* All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include "fsl_rdc_sema42.h"
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/******************************************************************************
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* Definitions
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*****************************************************************************/
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/* Component ID definition, used by tools. */
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#ifndef FSL_COMPONENT_ID
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#define FSL_COMPONENT_ID "platform.drivers.rdc_sema42"
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#endif
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/* The first number write to RSTGDP when reset RDC_SEMA42 gate. */
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#define RDC_SEMA42_GATE_RESET_PATTERN_1 (0xE2U)
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/* The second number write to RSTGDP when reset RDC_SEMA42 gate. */
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#define RDC_SEMA42_GATE_RESET_PATTERN_2 (0x1DU)
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#if !defined(RDC_SEMAPHORE_GATE_COUNT)
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/* Compatible remap. */
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#define RDC_SEMAPHORE_GATE_LDOM(x) RDC_SEMAPHORE_GATE0_LDOM(x)
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#define RDC_SEMAPHORE_GATE_GTFSM(x) RDC_SEMAPHORE_GATE0_GTFSM(x)
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#define RDC_SEMAPHORE_GATE_LDOM_MASK RDC_SEMAPHORE_GATE0_LDOM_MASK
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#define RDC_SEMAPHORE_GATE_LDOM_SHIFT RDC_SEMAPHORE_GATE0_LDOM_SHIFT
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#endif
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/*******************************************************************************
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* Prototypes
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******************************************************************************/
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/*!
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* @brief Get instance number for RDC_SEMA42 module.
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*
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* @param base RDC_SEMA42 peripheral base address.
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*/
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uint32_t RDC_SEMA42_GetInstance(RDC_SEMAPHORE_Type *base);
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/*******************************************************************************
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* Variables
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******************************************************************************/
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/*! @brief Pointers to sema42 bases for each instance. */
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static RDC_SEMAPHORE_Type *const s_sema42Bases[] = RDC_SEMAPHORE_BASE_PTRS;
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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#if defined(RDC_SEMA42_CLOCKS)
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/*! @brief Pointers to sema42 clocks for each instance. */
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static const clock_ip_name_t s_sema42Clocks[] = RDC_SEMA42_CLOCKS;
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#endif
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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/******************************************************************************
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* CODE
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*****************************************************************************/
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uint32_t RDC_SEMA42_GetInstance(RDC_SEMAPHORE_Type *base)
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{
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uint32_t instance;
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/* Find the instance index from base address mappings. */
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for (instance = 0; instance < ARRAY_SIZE(s_sema42Bases); instance++)
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{
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if (s_sema42Bases[instance] == base)
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{
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break;
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}
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}
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assert(instance < ARRAY_SIZE(s_sema42Bases));
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return instance;
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}
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/*!
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* brief Initializes the RDC_SEMA42 module.
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*
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* This function initializes the RDC_SEMA42 module. It only enables the clock but does
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* not reset the gates because the module might be used by other processors
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* at the same time. To reset the gates, call either RDC_SEMA42_ResetGate or
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* RDC_SEMA42_ResetAllGates function.
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*
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* param base RDC_SEMA42 peripheral base address.
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*/
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void RDC_SEMA42_Init(RDC_SEMAPHORE_Type *base)
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{
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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#if defined(RDC_SEMA42_CLOCKS)
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CLOCK_EnableClock(s_sema42Clocks[RDC_SEMA42_GetInstance(base)]);
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#endif
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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}
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/*!
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* brief De-initializes the RDC_SEMA42 module.
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*
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* This function de-initializes the RDC_SEMA42 module. It only disables the clock.
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*
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* param base RDC_SEMA42 peripheral base address.
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*/
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void RDC_SEMA42_Deinit(RDC_SEMAPHORE_Type *base)
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{
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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#if defined(RDC_SEMA42_CLOCKS)
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CLOCK_DisableClock(s_sema42Clocks[RDC_SEMA42_GetInstance(base)]);
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#endif
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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}
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/*!
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* brief Tries to lock the RDC_SEMA42 gate.
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*
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* This function tries to lock the specific RDC_SEMA42 gate. If the gate has been
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* locked by another processor, this function returns an error code.
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*
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* param base RDC_SEMA42 peripheral base address.
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* param gateNum Gate number to lock.
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* param masterIndex Current processor master index.
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* param domainId Current processor domain ID.
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*
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* retval kStatus_Success Lock the sema42 gate successfully.
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* retval kStatus_Failed Sema42 gate has been locked by another processor.
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*/
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status_t RDC_SEMA42_TryLock(RDC_SEMAPHORE_Type *base, uint8_t gateNum, uint8_t masterIndex, uint8_t domainId)
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{
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assert(gateNum < RDC_SEMA42_GATE_COUNT);
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status_t status = kStatus_Success;
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uint8_t regGate;
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++masterIndex;
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regGate = (uint8_t)(RDC_SEMAPHORE_GATE_LDOM(domainId) | RDC_SEMAPHORE_GATE_GTFSM(masterIndex));
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/* Try to lock. */
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RDC_SEMA42_GATEn(base, gateNum) = masterIndex;
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/* Check locked or not. */
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if (regGate != RDC_SEMA42_GATEn(base, gateNum))
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{
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status = kStatus_Fail;
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}
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return status;
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}
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/*!
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* brief Locks the RDC_SEMA42 gate.
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*
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* This function locks the specific RDC_SEMA42 gate. If the gate has been
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* locked by other processors, this function waits until it is unlocked and then
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* lock it.
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*
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* param base RDC_SEMA42 peripheral base address.
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* param gateNum Gate number to lock.
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* param masterIndex Current processor master index.
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* param domainId Current processor domain ID.
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*/
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void RDC_SEMA42_Lock(RDC_SEMAPHORE_Type *base, uint8_t gateNum, uint8_t masterIndex, uint8_t domainId)
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{
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assert(gateNum < RDC_SEMA42_GATE_COUNT);
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uint8_t regGate;
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++masterIndex;
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regGate = (uint8_t)(RDC_SEMAPHORE_GATE_LDOM(domainId) | RDC_SEMAPHORE_GATE_GTFSM(masterIndex));
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while (regGate != RDC_SEMA42_GATEn(base, gateNum))
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{
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/* Wait for unlocked status. */
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while (0U != (RDC_SEMA42_GATEn(base, gateNum) & RDC_SEMAPHORE_GATE_GTFSM_MASK))
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{
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}
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/* Lock the gate. */
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RDC_SEMA42_GATEn(base, gateNum) = masterIndex;
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}
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}
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/*!
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* brief Gets which domain has currently locked the gate.
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*
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* param base RDC_SEMA42 peripheral base address.
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* param gateNum Gate number.
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*
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* return Return -1 if the gate is not locked by any domain, otherwise return the
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* domain ID.
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*/
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int32_t RDC_SEMA42_GetLockDomainID(RDC_SEMAPHORE_Type *base, uint8_t gateNum)
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{
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assert(gateNum < RDC_SEMA42_GATE_COUNT);
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int32_t ret;
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uint8_t regGate = RDC_SEMA42_GATEn(base, gateNum);
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/* Current gate is not locked. */
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if (0U == (regGate & RDC_SEMAPHORE_GATE_GTFSM_MASK))
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{
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ret = -1;
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}
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else
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{
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ret = (int32_t)((uint8_t)((regGate & RDC_SEMAPHORE_GATE_LDOM_MASK) >> RDC_SEMAPHORE_GATE_LDOM_SHIFT));
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}
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return ret;
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}
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/*!
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* brief Resets the RDC_SEMA42 gate to an unlocked status.
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*
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* This function resets a RDC_SEMA42 gate to an unlocked status.
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*
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* param base RDC_SEMA42 peripheral base address.
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* param gateNum Gate number.
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*
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* retval kStatus_Success RDC_SEMA42 gate is reset successfully.
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* retval kStatus_Failed Some other reset process is ongoing.
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*/
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status_t RDC_SEMA42_ResetGate(RDC_SEMAPHORE_Type *base, uint8_t gateNum)
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{
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status_t status;
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/*
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* Reset all gates if gateNum >= RDC_SEMA42_GATE_NUM_RESET_ALL
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* Reset specific gate if gateNum < RDC_SEMA42_GATE_COUNT
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*/
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/* Check whether some reset is ongoing. */
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if (0U != (base->RSTGT_R & RDC_SEMAPHORE_RSTGT_R_RSTGSM_MASK))
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{
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status = kStatus_Fail;
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}
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else
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{
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/* First step. */
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base->RSTGT_W = RDC_SEMAPHORE_RSTGT_W_RSTGDP(RDC_SEMA42_GATE_RESET_PATTERN_1);
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/* Second step. */
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base->RSTGT_W =
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RDC_SEMAPHORE_RSTGT_W_RSTGDP(RDC_SEMA42_GATE_RESET_PATTERN_2) | RDC_SEMAPHORE_RSTGT_W_RSTGTN(gateNum);
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status = kStatus_Success;
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}
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return status;
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}
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