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https://github.com/RT-Thread/rt-thread.git
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fe2b124345
Support for ARM64 ASID to enhance virtual memory management efficiency by reducing the need for TLB flushes during address space switches. These changes improve performance especially for multi-process systems. Changes: - Added `ARCH_USING_ASID` configuration in `libcpu/aarch64/Kconfig`. - Defined ASID-related constants in `mmu.h`. - Updated `TLBI_ARG` macro to include ASID manipulation. - Implemented ASID allocation mechanism with spinlock synchronization. - Enhanced TLB invalidation to support ASID-specific operations. - Modified `rt_hw_aspace_switch` to use ASIDs when switching address spaces. - Adjusted debug logging and function documentation to reflect ASID usage. - Refactored AArch64 MMU and TLB handling for ASID integration. Signed-off-by: Shell <smokewood@qq.com>
92 lines
2.4 KiB
C
92 lines
2.4 KiB
C
/*
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* Copyright (c) 2006-2022, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2022-11-28 WangXiaoyao the first version
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*/
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#ifndef __TLB_H__
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#define __TLB_H__
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#include <rtthread.h>
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#include <stddef.h>
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#include <stdint.h>
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#include "mm_aspace.h"
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#include "mmu.h"
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#define TLBI_ARG(addr, asid) \
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({ \
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rt_ubase_t arg = (rt_ubase_t)(addr) >> ARCH_PAGE_SHIFT; \
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arg &= (1ull << 44) - 1; \
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arg |= (rt_ubase_t)(asid) << MMU_ASID_SHIFT; \
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(void *)arg; \
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})
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static inline void rt_hw_tlb_invalidate_all(void)
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{
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__asm__ volatile(
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// ensure updates to pte completed
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"dsb ishst\n"
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"tlbi vmalle1is\n"
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"dsb ish\n"
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// after tlb in new context, refresh inst
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"isb\n" ::
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: "memory");
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}
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static inline void rt_hw_tlb_invalidate_all_local(void)
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{
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__asm__ volatile(
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// ensure updates to pte completed
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"dsb nshst\n"
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"tlbi vmalle1is\n"
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"dsb nsh\n"
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// after tlb in new context, refresh inst
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"isb\n" ::
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: "memory");
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}
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static inline void rt_hw_tlb_invalidate_aspace(rt_aspace_t aspace)
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{
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#ifdef ARCH_USING_ASID
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__asm__ volatile(
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// ensure updates to pte completed
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"dsb nshst\n"
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"tlbi aside1is, %0\n"
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"dsb nsh\n"
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// after tlb in new context, refresh inst
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"isb\n" ::"r"(TLBI_ARG(0ul, aspace->asid))
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: "memory");
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#else
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rt_hw_tlb_invalidate_all();
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#endif
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}
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static inline void rt_hw_tlb_invalidate_page(rt_aspace_t aspace, void *start)
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{
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start = TLBI_ARG(start, 0);
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__asm__ volatile(
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"dsb ishst\n"
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"tlbi vaae1is, %0\n"
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"dsb ish\n"
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"isb\n" ::"r"(start)
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: "memory");
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}
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static inline void rt_hw_tlb_invalidate_range(rt_aspace_t aspace, void *start,
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size_t size, size_t stride)
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{
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if (size <= ARCH_PAGE_SIZE)
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{
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rt_hw_tlb_invalidate_page(aspace, start);
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}
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else
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{
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rt_hw_tlb_invalidate_aspace(aspace);
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}
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}
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#endif /* __TLB_H__ */
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