153 lines
9.1 KiB
C
153 lines
9.1 KiB
C
/*!
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\file gd32f10x_dbg.h
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\brief definitions for the DBG
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\version 2014-12-26, V1.0.0, firmware for GD32F10x
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\version 2017-06-20, V2.0.0, firmware for GD32F10x
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\version 2018-07-31, V2.1.0, firmware for GD32F10x
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*/
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/*
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Copyright (c) 2018, GigaDevice Semiconductor Inc.
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All rights reserved.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice, this
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list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation
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and/or other materials provided with the distribution.
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3. Neither the name of the copyright holder nor the names of its contributors
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may be used to endorse or promote products derived from this software without
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specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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OF SUCH DAMAGE.
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*/
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#ifndef GD32F10X_DBG_H
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#define GD32F10X_DBG_H
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#include "gd32f10x.h"
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/* DBG definitions */
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#define DBG DBG_BASE
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/* registers definitions */
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#define DBG_ID REG32(DBG + 0x00U) /*!< DBG_ID code register */
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#define DBG_CTL REG32(DBG + 0x04U) /*!< DBG control register */
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/* bits definitions */
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/* DBG_ID */
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#define DBG_ID_ID_CODE BITS(0,31) /*!< DBG ID code values */
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/* DBG_CTL */
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#define DBG_CTL_SLP_HOLD BIT(0) /*!< keep debugger connection during sleep mode */
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#define DBG_CTL_DSLP_HOLD BIT(1) /*!< keep debugger connection during deepsleep mode */
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#define DBG_CTL_STB_HOLD BIT(2) /*!< keep debugger connection during standby mode */
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#define DBG_CTL_TRACE_IOEN BIT(5) /*!< enable trace pin assignment */
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#define DBG_CTL_TRACE_MODE BITS(6,7) /*!< trace pin mode selection */
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#define DBG_CTL_FWDGT_HOLD BIT(8) /*!< debug FWDGT kept when core is halted */
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#define DBG_CTL_WWDGT_HOLD BIT(9) /*!< debug WWDGT kept when core is halted */
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#define DBG_CTL_TIMER0_HOLD BIT(10) /*!< hold TIMER0 counter when core is halted */
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#define DBG_CTL_TIMER1_HOLD BIT(11) /*!< hold TIMER1 counter when core is halted */
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#define DBG_CTL_TIMER2_HOLD BIT(12) /*!< hold TIMER2 counter when core is halted */
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#define DBG_CTL_TIMER3_HOLD BIT(13) /*!< hold TIMER3 counter when core is halted */
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#define DBG_CTL_CAN0_HOLD BIT(14) /*!< debug CAN0 kept when core is halted */
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#define DBG_CTL_I2C0_HOLD BIT(15) /*!< hold I2C0 smbus when core is halted */
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#define DBG_CTL_I2C1_HOLD BIT(16) /*!< hold I2C1 smbus when core is halted */
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#define DBG_CTL_TIMER4_HOLD BIT(17) /*!< hold TIMER4 counter when core is halted */
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#define DBG_CTL_TIMER5_HOLD BIT(18) /*!< hold TIMER5 counter when core is halted */
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#define DBG_CTL_TIMER6_HOLD BIT(19) /*!< hold TIMER6 counter when core is halted */
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#define DBG_CTL_TIMER7_HOLD BIT(20) /*!< hold TIMER7 counter when core is halted */
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#ifdef GD32F10x_CL
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#define DBG_CTL_CAN1_HOLD BIT(21) /*!< debug CAN1 kept when core is halted */
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#endif /* GD32F10x_CL */
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#ifdef GD32F10X_XD
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#define DBG_CTL_TIMER11_HOLD BIT(25) /*!< hold TIMER11 counter when core is halted */
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#define DBG_CTL_TIMER12_HOLD BIT(26) /*!< hold TIMER12 counter when core is halted */
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#define DBG_CTL_TIMER13_HOLD BIT(27) /*!< hold TIMER13 counter when core is halted */
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#define DBG_CTL_TIMER8_HOLD BIT(28) /*!< hold TIMER8 counter when core is halted */
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#define DBG_CTL_TIMER9_HOLD BIT(29) /*!< hold TIMER9 counter when core is halted */
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#define DBG_CTL_TIMER10_HOLD BIT(30) /*!< hold TIMER10 counter when core is halted */
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#endif /* GD32F10x_XD */
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/* constants definitions */
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/* debug hold when core is halted */
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typedef enum
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{
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DBG_FWDGT_HOLD = BIT(8), /*!< debug FWDGT kept when core is halted */
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DBG_WWDGT_HOLD = BIT(9), /*!< debug WWDGT kept when core is halted */
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DBG_TIMER0_HOLD = BIT(10), /*!< hold TIMER0 counter when core is halted */
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DBG_TIMER1_HOLD = BIT(11), /*!< hold TIMER1 counter when core is halted */
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DBG_TIMER2_HOLD = BIT(12), /*!< hold TIMER2 counter when core is halted */
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DBG_TIMER3_HOLD = BIT(13), /*!< hold TIMER3 counter when core is halted */
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DBG_CAN0_HOLD = BIT(14), /*!< debug CAN0 kept when core is halted */
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DBG_I2C0_HOLD = BIT(15), /*!< hold I2C0 smbus when core is halted */
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DBG_I2C1_HOLD = BIT(16), /*!< hold I2C1 smbus when core is halted */
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DBG_TIMER4_HOLD = BIT(17), /*!< hold TIMER4 counter when core is halted */
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DBG_TIMER5_HOLD = BIT(18), /*!< hold TIMER5 counter when core is halted */
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DBG_TIMER6_HOLD = BIT(19), /*!< hold TIMER6 counter when core is halted */
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DBG_TIMER7_HOLD = BIT(20), /*!< hold TIMER7 counter when core is halted */
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#ifdef GD32F10x_CL
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DBG_CAN1_HOLD = BIT(21), /*!< debug CAN1 kept when core is halted */
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#endif /* GD32F10x_CL */
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#if (defined(GD32F10x_XD) || defined(GD32F10x_CL))
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DBG_TIMER11_HOLD = BIT(25), /*!< hold TIMER11 counter when core is halted */
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DBG_TIMER12_HOLD = BIT(26), /*!< hold TIMER12 counter when core is halted */
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DBG_TIMER13_HOLD = BIT(27), /*!< hold TIMER13 counter when core is halted */
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DBG_TIMER8_HOLD = BIT(28), /*!< hold TIMER8 counter when core is halted */
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DBG_TIMER9_HOLD = BIT(29), /*!< hold TIMER9 counter when core is halted */
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DBG_TIMER10_HOLD = BIT(30), /*!< hold TIMER10 counter when core is halted */
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#endif /* GD32F10x_XD || GD32F10x_CL*/
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}dbg_periph_enum;
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/* DBG low power mode configurations */
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#define DBG_LOW_POWER_SLEEP DBG_CTL_SLP_HOLD /*!< keep debugger connection during sleep mode */
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#define DBG_LOW_POWER_DEEPSLEEP DBG_CTL_DSLP_HOLD /*!< keep debugger connection during deepsleep mode */
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#define DBG_LOW_POWER_STANDBY DBG_CTL_STB_HOLD /*!< keep debugger connection during standby mode */
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/* DBG_CTL0_TRACE_MODE configurations */
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#define CTL_TRACE_MODE(regval) (BITS(6,7) & ((uint32_t)(regval) << 6U))
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#define TRACE_MODE_ASYNC CTL_TRACE_MODE(0) /*!< trace pin used for async mode */
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#define TRACE_MODE_SYNC_DATASIZE_1 CTL_TRACE_MODE(1) /*!< trace pin used for sync mode and data size is 1 */
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#define TRACE_MODE_SYNC_DATASIZE_2 CTL_TRACE_MODE(2) /*!< trace pin used for sync mode and data size is 2 */
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#define TRACE_MODE_SYNC_DATASIZE_4 CTL_TRACE_MODE(3) /*!< trace pin used for sync mode and data size is 4 */
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/* function declarations */
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/* read DBG_ID code register */
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uint32_t dbg_id_get(void);
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/* low power behavior configuration */
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/* enable low power behavior when the MCU is in debug mode */
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void dbg_low_power_enable(uint32_t dbg_low_power);
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/* disable low power behavior when the MCU is in debug mode */
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void dbg_low_power_disable(uint32_t dbg_low_power);
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/* peripheral behavior configuration */
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/* enable peripheral behavior when the MCU is in debug mode */
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void dbg_periph_enable(dbg_periph_enum dbg_periph);
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/* disable peripheral behavior when the MCU is in debug mode */
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void dbg_periph_disable(dbg_periph_enum dbg_periph);
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/* trace pin assignment configuration */
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/* enable trace pin assignment */
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void dbg_trace_pin_enable(void);
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/* disable trace pin assignment */
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void dbg_trace_pin_disable(void);
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/* set trace pin mode */
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void dbg_trace_pin_mode_set(uint32_t trace_mode);
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#endif /* GD32F10x_DBG_H */
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