215 lines
5.7 KiB
ArmAsm
215 lines
5.7 KiB
ArmAsm
/*
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* Copyright (c) 2006-2018, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2021-09-09 WCH the first version
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*/
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#include "cpuport.h"
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/*
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* #ifdef RT_USING_SMP
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* void rt_hw_context_switch_to(rt_ubase_t to, stuct rt_thread *to_thread);
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* #else
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* void rt_hw_context_switch_to(rt_ubase_t to);
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* #endif
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* a0 --> to
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* a1 --> to_thread
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*/
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.globl rt_hw_context_switch_to
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rt_hw_context_switch_to:
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/* first save interrupt stack */
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la t0, _eusrstack
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addi t0, t0, -512
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csrw mscratch,t0
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LOAD sp, (a0)
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LOAD a0, 2 * REGBYTES(sp)
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csrw mstatus, a0
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j rt_hw_context_switch_exit
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/*
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* void rt_hw_context_switch(rt_ubase_t from, rt_ubase_t to);
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* a0 --> from
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* a1 --> to
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*/
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.globl rt_hw_context_switch
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rt_hw_context_switch:
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/* switch in thread */
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#ifdef ARCH_RISCV_FPU
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addi sp, sp, -32*FREGBYTES
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FSTORE f0, 0 * FREGBYTES(sp)
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FSTORE f1, 1 * FREGBYTES(sp)
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FSTORE f2, 2 * FREGBYTES(sp)
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FSTORE f3, 3 * FREGBYTES(sp)
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FSTORE f4, 4 * FREGBYTES(sp)
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FSTORE f5, 5 * FREGBYTES(sp)
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FSTORE f6, 6 * FREGBYTES(sp)
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FSTORE f7, 7 * FREGBYTES(sp)
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FSTORE f8, 8 * FREGBYTES(sp)
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FSTORE f9, 9 * FREGBYTES(sp)
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FSTORE f10, 10 * FREGBYTES(sp)
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FSTORE f11, 11 * FREGBYTES(sp)
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FSTORE f12, 12 * FREGBYTES(sp)
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FSTORE f13, 13 * FREGBYTES(sp)
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FSTORE f14, 14 * FREGBYTES(sp)
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FSTORE f15, 15 * FREGBYTES(sp)
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FSTORE f16, 16 * FREGBYTES(sp)
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FSTORE f17, 17 * FREGBYTES(sp)
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FSTORE f18, 18 * FREGBYTES(sp)
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FSTORE f19, 19 * FREGBYTES(sp)
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FSTORE f20, 20 * FREGBYTES(sp)
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FSTORE f21, 21 * FREGBYTES(sp)
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FSTORE f22, 22 * FREGBYTES(sp)
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FSTORE f23, 23 * FREGBYTES(sp)
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FSTORE f24, 24 * FREGBYTES(sp)
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FSTORE f25, 25 * FREGBYTES(sp)
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FSTORE f26, 26 * FREGBYTES(sp)
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FSTORE f27, 27 * FREGBYTES(sp)
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FSTORE f28, 28 * FREGBYTES(sp)
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FSTORE f29, 29 * FREGBYTES(sp)
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FSTORE f30, 30 * FREGBYTES(sp)
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FSTORE f31, 31 * FREGBYTES(sp)
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#endif
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addi sp, sp, -32 * REGBYTES
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/* save from sp */
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STORE sp, 0(a0)
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/* save ra to epc */
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STORE x1, 0 * REGBYTES(sp)
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STORE x1, 1 * REGBYTES(sp)
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STORE x5, 5 * REGBYTES(sp)
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csrr t0, mstatus
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andi t0, t0, 8
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/* if MIE be enabled,set MPIE */
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beqz t0, 1f
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li t0, 0x80
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1: STORE t0, 2 * REGBYTES(sp)
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STORE x4, 4 * REGBYTES(sp)
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STORE x6, 6 * REGBYTES(sp)
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STORE x7, 7 * REGBYTES(sp)
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STORE x8, 8 * REGBYTES(sp)
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STORE x9, 9 * REGBYTES(sp)
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STORE x10, 10 * REGBYTES(sp)
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STORE x11, 11 * REGBYTES(sp)
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STORE x12, 12 * REGBYTES(sp)
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STORE x13, 13 * REGBYTES(sp)
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STORE x14, 14 * REGBYTES(sp)
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STORE x15, 15 * REGBYTES(sp)
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STORE x16, 16 * REGBYTES(sp)
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STORE x17, 17 * REGBYTES(sp)
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STORE x18, 18 * REGBYTES(sp)
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STORE x19, 19 * REGBYTES(sp)
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STORE x20, 20 * REGBYTES(sp)
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STORE x21, 21 * REGBYTES(sp)
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STORE x22, 22 * REGBYTES(sp)
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STORE x23, 23 * REGBYTES(sp)
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STORE x24, 24 * REGBYTES(sp)
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STORE x25, 25 * REGBYTES(sp)
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STORE x26, 26 * REGBYTES(sp)
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STORE x27, 27 * REGBYTES(sp)
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STORE x28, 28 * REGBYTES(sp)
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STORE x29, 29 * REGBYTES(sp)
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STORE x30, 30 * REGBYTES(sp)
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STORE x31, 31 * REGBYTES(sp)
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/* get "to" thread sp */
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LOAD sp, 0(a1)
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j rt_hw_context_switch_exit
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.global rt_hw_context_switch_exit
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rt_hw_context_switch_exit:
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/* resw ra to mepc */
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LOAD a0, 0 * REGBYTES(sp)
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csrw mepc, a0
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LOAD x1, 1 * REGBYTES(sp)
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/* keep machine mode */
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li a0, 0x7800
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csrs mstatus, a0
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/* resume MPIE */
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LOAD a0, 2*REGBYTES(sp)
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csrs mstatus, a0
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LOAD x4, 4 * REGBYTES(sp)
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LOAD x5, 5 * REGBYTES(sp)
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LOAD x6, 6 * REGBYTES(sp)
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LOAD x7, 7 * REGBYTES(sp)
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LOAD x8, 8 * REGBYTES(sp)
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LOAD x9, 9 * REGBYTES(sp)
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LOAD x10, 10 * REGBYTES(sp)
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LOAD x11, 11 * REGBYTES(sp)
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LOAD x12, 12 * REGBYTES(sp)
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LOAD x13, 13 * REGBYTES(sp)
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LOAD x14, 14 * REGBYTES(sp)
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LOAD x15, 15 * REGBYTES(sp)
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LOAD x16, 16 * REGBYTES(sp)
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LOAD x17, 17 * REGBYTES(sp)
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LOAD x18, 18 * REGBYTES(sp)
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LOAD x19, 19 * REGBYTES(sp)
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LOAD x20, 20 * REGBYTES(sp)
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LOAD x21, 21 * REGBYTES(sp)
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LOAD x22, 22 * REGBYTES(sp)
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LOAD x23, 23 * REGBYTES(sp)
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LOAD x24, 24 * REGBYTES(sp)
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LOAD x25, 25 * REGBYTES(sp)
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LOAD x26, 26 * REGBYTES(sp)
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LOAD x27, 27 * REGBYTES(sp)
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LOAD x28, 28 * REGBYTES(sp)
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LOAD x29, 29 * REGBYTES(sp)
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LOAD x30, 30 * REGBYTES(sp)
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LOAD x31, 31 * REGBYTES(sp)
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addi sp, sp, 32 * REGBYTES
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/* load float reg */
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#ifdef ARCH_RISCV_FPU
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FLOAD f0, 0 * FREGBYTES(sp)
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FLOAD f1, 1 * FREGBYTES(sp)
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FLOAD f2, 2 * FREGBYTES(sp)
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FLOAD f3, 3 * FREGBYTES(sp)
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FLOAD f4, 4 * FREGBYTES(sp)
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FLOAD f5, 5 * FREGBYTES(sp)
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FLOAD f6, 6 * FREGBYTES(sp)
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FLOAD f7, 7 * FREGBYTES(sp)
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FLOAD f8, 8 * FREGBYTES(sp)
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FLOAD f9, 9 * FREGBYTES(sp)
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FLOAD f10, 10 * FREGBYTES(sp)
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FLOAD f11, 11 * FREGBYTES(sp)
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FLOAD f12, 12 * FREGBYTES(sp)
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FLOAD f13, 13 * FREGBYTES(sp)
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FLOAD f14, 14 * FREGBYTES(sp)
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FLOAD f15, 15 * FREGBYTES(sp)
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FLOAD f16, 16 * FREGBYTES(sp)
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FLOAD f17, 17 * FREGBYTES(sp)
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FLOAD f18, 18 * FREGBYTES(sp)
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FLOAD f19, 19 * FREGBYTES(sp)
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FLOAD f20, 20 * FREGBYTES(sp)
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FLOAD f21, 21 * FREGBYTES(sp)
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FLOAD f22, 22 * FREGBYTES(sp)
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FLOAD f23, 23 * FREGBYTES(sp)
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FLOAD f24, 24 * FREGBYTES(sp)
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FLOAD f25, 25 * FREGBYTES(sp)
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FLOAD f26, 26 * FREGBYTES(sp)
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FLOAD f27, 27 * FREGBYTES(sp)
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FLOAD f28, 28 * FREGBYTES(sp)
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FLOAD f29, 29 * FREGBYTES(sp)
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FLOAD f30, 30 * FREGBYTES(sp)
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FLOAD f31, 31 * FREGBYTES(sp)
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addi sp, sp, 32 * FREGBYTES
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#endif
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mret
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