242 lines
6.0 KiB
C
242 lines
6.0 KiB
C
/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2017-12-04 Haley the first version
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*/
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#include <rtthread.h>
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#include <rtdevice.h>
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#include "am_mcu_apollo.h"
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/* I2C0 */
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#define AM_I2C0_IOM_INST 0
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#define I2C0_GPIO_SCL 5
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#define I2C0_GPIO_CFG_SCK AM_HAL_PIN_5_M0SCL
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#define I2C0_GPIO_SDA 6
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#define I2C0_GPIO_CFG_SDA AM_HAL_PIN_6_M0SDA
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/* I2C2 */
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#define AM_I2C2_IOM_INST 2
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#define I2C2_GPIO_SCL 27
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#define I2C2_GPIO_CFG_SCK AM_HAL_PIN_27_M2SCL
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#define I2C2_GPIO_SDA 25
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#define I2C2_GPIO_CFG_SDA AM_HAL_PIN_25_M2SDA
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/* I2C3 */
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#define AM_I2C3_IOM_INST 3
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#define I2C3_GPIO_SCL 42
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#define I2C3_GPIO_CFG_SCK AM_HAL_PIN_42_M3SCL
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#define I2C3_GPIO_SDA 43
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#define I2C3_GPIO_CFG_SDA AM_HAL_PIN_43_M3SDA
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/* I2C4 */
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#define AM_I2C4_IOM_INST 4
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#define I2C4_GPIO_SCL 39
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#define I2C4_GPIO_CFG_SCK AM_HAL_PIN_39_M4SCL
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#define I2C4_GPIO_SDA 40
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#define I2C4_GPIO_CFG_SDA AM_HAL_PIN_40_M4SDA
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static am_hal_iom_config_t g_sIOMConfig =
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{
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AM_HAL_IOM_I2CMODE, // ui32InterfaceMode
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AM_HAL_IOM_100KHZ, // ui32ClockFrequency
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0, // bSPHA
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0, // bSPOL
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4, // ui8WriteThreshold
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60, // ui8ReadThreshold
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};
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/* AM i2c driver */
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struct am_i2c_bus
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{
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struct rt_i2c_bus_device parent;
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rt_uint32_t u32Module;
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};
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//connect am drv to rt drv.
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rt_size_t rt_i2c_master_xfer(struct rt_i2c_bus_device *bus,
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struct rt_i2c_msg *msgs,
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rt_uint32_t num)
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{
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struct am_i2c_bus * am_i2c_bus = (struct am_i2c_bus *)bus;
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struct rt_i2c_msg *msg;
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int i;
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rt_uint32_t msg_len = 0;
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for (i = 0; i < num; i++)
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{
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msg = &msgs[i];
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if (msg->flags == RT_I2C_RD)
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{
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am_hal_iom_i2c_read(am_i2c_bus->u32Module, msg->addr, (uint32_t *)msg->buf, msg->len, AM_HAL_IOM_RAW);
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msg_len += msg->len;
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}
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else if(msg->flags == RT_I2C_WR)
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{
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am_hal_iom_i2c_write(am_i2c_bus->u32Module, msg->addr, (uint32_t *)msg->buf, msg->len, AM_HAL_IOM_RAW);
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msg_len += (msg->len - 1);
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}
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}
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return msg_len;
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}
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rt_err_t rt_i2c_bus_control(struct rt_i2c_bus_device *bus,
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rt_uint32_t cmd,
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rt_uint32_t arg)
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{
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struct am_i2c_bus * am_i2c_bus = (struct am_i2c_bus *)bus;
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//rt_uint32_t ctrl_arg = (rt_uint32_t)(arg);
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RT_ASSERT(bus != RT_NULL);
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am_i2c_bus = (struct am_i2c_bus *)bus->parent.user_data;
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RT_ASSERT(am_i2c_bus != RT_NULL);
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switch (cmd)
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{
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/* I2C config */
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case RT_DEVICE_CTRL_CONFIG :
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break;
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}
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return RT_EOK;
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}
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static const struct rt_i2c_bus_device_ops am_i2c_ops =
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{
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rt_i2c_master_xfer,
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RT_NULL,
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rt_i2c_bus_control
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};
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#ifdef RT_USING_I2C0
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static struct am_i2c_bus am_i2c_bus_0 =
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{
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{0},
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AM_I2C0_IOM_INST
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};
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#endif
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#ifdef RT_USING_I2C1
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static struct am_i2c_bus am_i2c_bus_1 =
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{
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{1},
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AM_I2C1_IOM_INST
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};
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#endif
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#ifdef RT_USING_I2C2
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static struct am_i2c_bus am_i2c_bus_2 =
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{
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{2},
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AM_I2C2_IOM_INST
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};
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#endif
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#ifdef RT_USING_I2C3
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static struct am_i2c_bus am_i2c_bus_3 =
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{
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{3},
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AM_I2C3_IOM_INST
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};
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#endif
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#ifdef RT_USING_I2C4
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static struct am_i2c_bus am_i2c_bus_4 =
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{
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{4},
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AM_I2C4_IOM_INST
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};
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#endif
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int rt_i2c_init(void)
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{
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struct am_i2c_bus* am_i2c;
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#ifdef RT_USING_I2C0
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/* init i2c gpio */
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am_hal_gpio_pin_config(I2C0_GPIO_SCL, I2C0_GPIO_CFG_SCK | AM_HAL_GPIO_PULL6K);
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am_hal_gpio_pin_config(I2C0_GPIO_SDA, I2C0_GPIO_CFG_SDA | AM_HAL_GPIO_PULL6K);
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/* Initialize IOM 0 in I2C mode at 100KHz */
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am_hal_iom_pwrctrl_enable(AM_I2C0_IOM_INST);
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g_sIOMConfig.ui32ClockFrequency = AM_HAL_IOM_100KHZ;
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am_hal_iom_config(AM_I2C0_IOM_INST, &g_sIOMConfig);
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am_hal_iom_enable(AM_I2C0_IOM_INST);
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/* init i2c bus device */
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am_i2c = &am_i2c_bus_0;
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am_i2c->parent.ops = &am_i2c_ops;
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rt_i2c_bus_device_register(&am_i2c->parent, "i2c0");
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#endif
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#ifdef RT_USING_I2C2
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/* init i2c gpio */
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am_hal_gpio_pin_config(I2C2_GPIO_SCL, I2C2_GPIO_CFG_SCK | AM_HAL_GPIO_PULL6K);
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am_hal_gpio_pin_config(I2C2_GPIO_SDA, I2C2_GPIO_CFG_SDA | AM_HAL_GPIO_PULL6K);
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/* Initialize IOM 2 in I2C mode at 400KHz */
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am_hal_iom_pwrctrl_enable(AM_I2C2_IOM_INST);
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g_sIOMConfig.ui32ClockFrequency = AM_HAL_IOM_400KHZ;
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am_hal_iom_config(AM_I2C2_IOM_INST, &g_sIOMConfig);
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am_hal_iom_enable(AM_I2C2_IOM_INST);
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/* init i2c bus device */
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am_i2c = &am_i2c_bus_2;
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am_i2c->parent.ops = &am_i2c_ops;
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rt_i2c_bus_device_register(&am_i2c->parent, "i2c2");
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#endif
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#ifdef RT_USING_I2C3
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/* init i2c gpio */
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am_hal_gpio_pin_config(I2C3_GPIO_SCL, I2C3_GPIO_CFG_SCK | AM_HAL_GPIO_PULL6K);
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am_hal_gpio_pin_config(I2C3_GPIO_SDA, I2C3_GPIO_CFG_SDA | AM_HAL_GPIO_PULL6K);
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/* Initialize IOM 3 in I2C mode at 400KHz */
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am_hal_iom_pwrctrl_enable(AM_I2C3_IOM_INST);
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g_sIOMConfig.ui32ClockFrequency = AM_HAL_IOM_400KHZ;
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am_hal_iom_config(AM_I2C3_IOM_INST, &g_sIOMConfig);
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am_hal_iom_enable(AM_I2C3_IOM_INST);
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/* init i2c bus device */
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am_i2c = &am_i2c_bus_3;
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am_i2c->parent.ops = &am_i2c_ops;
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rt_i2c_bus_device_register(&am_i2c->parent, "i2c3");
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#endif
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#ifdef RT_USING_I2C4
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/* init i2c gpio */
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am_hal_gpio_pin_config(I2C4_GPIO_SCL, I2C4_GPIO_CFG_SCK | AM_HAL_GPIO_PULL6K);
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am_hal_gpio_pin_config(I2C4_GPIO_SDA, I2C4_GPIO_CFG_SDA | AM_HAL_GPIO_PULL6K);
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/* Initialize IOM 4 in I2C mode at 400KHz */
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am_hal_iom_pwrctrl_enable(AM_I2C4_IOM_INST);
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g_sIOMConfig.ui32ClockFrequency = AM_HAL_IOM_400KHZ;
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am_hal_iom_config(AM_I2C4_IOM_INST, &g_sIOMConfig);
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am_hal_iom_enable(AM_I2C4_IOM_INST);
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/* init i2c bus device */
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am_i2c = &am_i2c_bus_4;
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am_i2c->parent.ops = &am_i2c_ops;
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rt_i2c_bus_device_register(&am_i2c->parent, "i2c4");
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#endif
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//rt_kprintf("i2c_init!\n");
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return 0;
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}
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#ifdef RT_USING_COMPONENTS_INIT
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INIT_BOARD_EXPORT(rt_i2c_init);
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#endif
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/*@}*/
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