698 lines
28 KiB
C
698 lines
28 KiB
C
/**********************************************************************
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* $Id$ lpc177x_8x_uart.h 2011-06-02
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*//**
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* @file lpc177x_8x_uart.h
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* @brief Contains all macro definitions and function prototypes
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* support for UART firmware library on LPC177x_8x
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* @version 1.0
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* @date 02. June. 2011
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* @author NXP MCU SW Application Team
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*
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* Copyright(C) 2011, NXP Semiconductor
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* All rights reserved.
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*
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***********************************************************************
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* Software that is described herein is for illustrative purposes only
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* which provides customers with programming information regarding the
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* products. This software is supplied "AS IS" without any warranties.
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* NXP Semiconductors assumes no responsibility or liability for the
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* use of the software, conveys no license or title under any patent,
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* copyright, or mask work right to the product. NXP Semiconductors
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* reserves the right to make changes in the software without
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* notification. NXP Semiconductors also make no representation or
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* warranty that such application will be suitable for the specified
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* use without further testing or modification.
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**********************************************************************/
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/* Peripheral group ----------------------------------------------------------- */
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/** @defgroup UART UART (Universal Asynchronous Receiver/Transmitter)
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* @ingroup LPC177x_8xCMSIS_FwLib_Drivers
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* @{
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*/
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#ifndef __LPC177X_8X_UART_H_
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#define __LPC177X_8X_UART_H_
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/* Includes ------------------------------------------------------------------- */
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#include "LPC177x_8x.h"
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#include "lpc_types.h"
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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/* Public Macros -------------------------------------------------------------- */
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/** @defgroup UART_Public_Macros UART Public Macros
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* @{
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*/
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/** UART time-out definitions in case of using Read() and Write function
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* with Blocking Flag mode
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*/
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#define UART_BLOCKING_TIMEOUT (0xFFFFFFFFUL)
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/**
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* @}
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*/
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/* Private Macros ------------------------------------------------------------- */
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/** @defgroup UART_Private_Macros UART Private Macros
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* @{
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*/
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/* Accepted Error baud rate value (in percent unit) */
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#define UART_ACCEPTED_BAUDRATE_ERROR (3) /*!< Acceptable UART baudrate error */
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/* --------------------- BIT DEFINITIONS -------------------------------------- */
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/*********************************************************************//**
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* Macro defines for Macro defines for UARTn Receiver Buffer Register
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**********************************************************************/
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/** UART Received Buffer mask bit (8 bits) */
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#define UART_RBR_MASKBIT ((uint8_t)0xFF)
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/*********************************************************************//**
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* Macro defines for Macro defines for UARTn Transmit Holding Register
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**********************************************************************/
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/** UART Transmit Holding mask bit (8 bits) */
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#define UART_THR_MASKBIT ((uint8_t)0xFF)
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/*********************************************************************//**
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* Macro defines for Macro defines for UARTn Divisor Latch LSB register
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**********************************************************************/
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/** Macro for loading least significant halfs of divisors */
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#define UART_LOAD_DLL(div) ((div) & 0xFF)
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/** Divisor latch LSB bit mask */
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#define UART_DLL_MASKBIT ((uint8_t)0xFF)
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/*********************************************************************//**
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* Macro defines for Macro defines for UARTn Divisor Latch MSB register
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**********************************************************************/
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/** Divisor latch MSB bit mask */
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#define UART_DLM_MASKBIT ((uint8_t)0xFF)
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/** Macro for loading most significant halfs of divisors */
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#define UART_LOAD_DLM(div) (((div) >> 8) & 0xFF)
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/*********************************************************************//**
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* Macro defines for Macro defines for UART interrupt enable register
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**********************************************************************/
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/** RBR Interrupt enable*/
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#define UART_IER_RBRINT_EN ((uint32_t)(1<<0))
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/** THR Interrupt enable*/
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#define UART_IER_THREINT_EN ((uint32_t)(1<<1))
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/** RX line status interrupt enable*/
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#define UART_IER_RLSINT_EN ((uint32_t)(1<<2))
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/** Modem status interrupt enable */
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#define UART1_IER_MSINT_EN ((uint32_t)(1<<3))
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/** CTS1 signal transition interrupt enable */
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#define UART1_IER_CTSINT_EN ((uint32_t)(1<<7))
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/** Enables the end of auto-baud interrupt */
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#define UART_IER_ABEOINT_EN ((uint32_t)(1<<8))
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/** Enables the auto-baud time-out interrupt */
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#define UART_IER_ABTOINT_EN ((uint32_t)(1<<9))
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/** UART interrupt enable register bit mask */
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#define UART_IER_BITMASK ((uint32_t)(0x307))
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/** UART1 interrupt enable register bit mask */
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#define UART1_IER_BITMASK ((uint32_t)(0x38F))
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/*********************************************************************//**
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* Macro defines for Macro defines for UART interrupt identification register
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**********************************************************************/
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/** Interrupt Status - Active low */
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#define UART_IIR_INTSTAT_PEND ((uint32_t)(1<<0))
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/** Interrupt identification: Receive line status*/
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#define UART_IIR_INTID_RLS ((uint32_t)(3<<1))
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/** Interrupt identification: Receive data available*/
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#define UART_IIR_INTID_RDA ((uint32_t)(2<<1))
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/** Interrupt identification: Character time-out indicator*/
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#define UART_IIR_INTID_CTI ((uint32_t)(6<<1))
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/** Interrupt identification: THRE interrupt*/
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#define UART_IIR_INTID_THRE ((uint32_t)(1<<1))
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/** Interrupt identification: Modem interrupt*/
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#define UART1_IIR_INTID_MODEM ((uint32_t)(0<<1))
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/** Interrupt identification: Interrupt ID mask */
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#define UART_IIR_INTID_MASK ((uint32_t)(7<<1))
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/** These bits are equivalent to UnFCR[0] */
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#define UART_IIR_FIFO_EN ((uint32_t)(3<<6))
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/** End of auto-baud interrupt */
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#define UART_IIR_ABEO_INT ((uint32_t)(1<<8))
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/** Auto-baud time-out interrupt */
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#define UART_IIR_ABTO_INT ((uint32_t)(1<<9))
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/** UART interrupt identification register bit mask */
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#define UART_IIR_BITMASK ((uint32_t)(0x3CF))
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/*********************************************************************//**
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* Macro defines for Macro defines for UART FIFO control register
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**********************************************************************/
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/** UART FIFO enable */
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#define UART_FCR_FIFO_EN ((uint8_t)(1<<0))
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/** UART FIFO RX reset */
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#define UART_FCR_RX_RS ((uint8_t)(1<<1))
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/** UART FIFO TX reset */
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#define UART_FCR_TX_RS ((uint8_t)(1<<2))
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/** UART DMA mode selection */
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#define UART_FCR_DMAMODE_SEL ((uint8_t)(1<<3))
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/** UART FIFO trigger level 0: 1 character */
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#define UART_FCR_TRG_LEV0 ((uint8_t)(0))
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/** UART FIFO trigger level 1: 4 character */
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#define UART_FCR_TRG_LEV1 ((uint8_t)(1<<6))
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/** UART FIFO trigger level 2: 8 character */
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#define UART_FCR_TRG_LEV2 ((uint8_t)(2<<6))
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/** UART FIFO trigger level 3: 14 character */
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#define UART_FCR_TRG_LEV3 ((uint8_t)(3<<6))
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/** UART FIFO control bit mask */
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#define UART_FCR_BITMASK ((uint8_t)(0xCF))
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#define UART_TX_FIFO_SIZE (16)
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/*********************************************************************//**
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* Macro defines for Macro defines for UART line control register
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**********************************************************************/
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/** UART 5 bit data mode */
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#define UART_LCR_WLEN5 ((uint8_t)(0))
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/** UART 6 bit data mode */
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#define UART_LCR_WLEN6 ((uint8_t)(1<<0))
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/** UART 7 bit data mode */
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#define UART_LCR_WLEN7 ((uint8_t)(2<<0))
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/** UART 8 bit data mode */
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#define UART_LCR_WLEN8 ((uint8_t)(3<<0))
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/** UART Two Stop Bits Select */
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#define UART_LCR_STOPBIT_SEL ((uint8_t)(1<<2))
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/** UART Parity Enable */
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#define UART_LCR_PARITY_EN ((uint8_t)(1<<3))
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/** UART Odd Parity Select */
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#define UART_LCR_PARITY_ODD ((uint8_t)(0))
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/** UART Even Parity Select */
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#define UART_LCR_PARITY_EVEN ((uint8_t)(1<<4))
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/** UART force 1 stick parity */
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#define UART_LCR_PARITY_F_1 ((uint8_t)(2<<4))
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/** UART force 0 stick parity */
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#define UART_LCR_PARITY_F_0 ((uint8_t)(3<<4))
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/** UART Transmission Break enable */
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#define UART_LCR_BREAK_EN ((uint8_t)(1<<6))
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/** UART Divisor Latches Access bit enable */
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#define UART_LCR_DLAB_EN ((uint8_t)(1<<7))
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/** UART line control bit mask */
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#define UART_LCR_BITMASK ((uint8_t)(0xFF))
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/*********************************************************************//**
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* Macro defines for Macro defines for UART1 Modem Control Register
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**********************************************************************/
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/** Source for modem output pin DTR */
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#define UART1_MCR_DTR_CTRL ((uint8_t)(1<<0))
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/** Source for modem output pin RTS */
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#define UART1_MCR_RTS_CTRL ((uint8_t)(1<<1))
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/** Loop back mode select */
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#define UART1_MCR_LOOPB_EN ((uint8_t)(1<<4))
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/** Enable Auto RTS flow-control */
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#define UART1_MCR_AUTO_RTS_EN ((uint8_t)(1<<6))
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/** Enable Auto CTS flow-control */
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#define UART1_MCR_AUTO_CTS_EN ((uint8_t)(1<<7))
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/** UART1 bit mask value */
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#define UART1_MCR_BITMASK ((uint8_t)(0x0F3))
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/*********************************************************************//**
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* Macro defines for Macro defines for UART line status register
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**********************************************************************/
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/** Line status register: Receive data ready*/
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#define UART_LSR_RDR ((uint8_t)(1<<0))
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/** Line status register: Overrun error*/
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#define UART_LSR_OE ((uint8_t)(1<<1))
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/** Line status register: Parity error*/
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#define UART_LSR_PE ((uint8_t)(1<<2))
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/** Line status register: Framing error*/
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#define UART_LSR_FE ((uint8_t)(1<<3))
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/** Line status register: Break interrupt*/
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#define UART_LSR_BI ((uint8_t)(1<<4))
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/** Line status register: Transmit holding register empty*/
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#define UART_LSR_THRE ((uint8_t)(1<<5))
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/** Line status register: Transmitter empty*/
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#define UART_LSR_TEMT ((uint8_t)(1<<6))
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/** Error in RX FIFO*/
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#define UART_LSR_RXFE ((uint8_t)(1<<7))
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/** UART Line status bit mask */
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#define UART_LSR_BITMASK ((uint8_t)(0xFF))
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/*********************************************************************//**
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* Macro defines for Macro defines for UART Modem (UART1 only) status register
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**********************************************************************/
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/** Set upon state change of input CTS */
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#define UART1_MSR_DELTA_CTS ((uint8_t)(1<<0))
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/** Set upon state change of input DSR */
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#define UART1_MSR_DELTA_DSR ((uint8_t)(1<<1))
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/** Set upon low to high transition of input RI */
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#define UART1_MSR_LO2HI_RI ((uint8_t)(1<<2))
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/** Set upon state change of input DCD */
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#define UART1_MSR_DELTA_DCD ((uint8_t)(1<<3))
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/** Clear To Send State */
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#define UART1_MSR_CTS ((uint8_t)(1<<4))
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/** Data Set Ready State */
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#define UART1_MSR_DSR ((uint8_t)(1<<5))
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/** Ring Indicator State */
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#define UART1_MSR_RI ((uint8_t)(1<<6))
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/** Data Carrier Detect State */
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#define UART1_MSR_DCD ((uint8_t)(1<<7))
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/** MSR register bit-mask value */
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#define UART1_MSR_BITMASK ((uint8_t)(0xFF))
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/*********************************************************************//**
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* Macro defines for Macro defines for UART Scratch Pad Register
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**********************************************************************/
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/** UART Scratch Pad bit mask */
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#define UART_SCR_BIMASK ((uint8_t)(0xFF))
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/*********************************************************************//**
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* Macro defines for Macro defines for UART Auto baudrate control register
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**********************************************************************/
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/** UART Auto-baud start */
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#define UART_ACR_START ((uint32_t)(1<<0))
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/** UART Auto baudrate Mode 1 */
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#define UART_ACR_MODE ((uint32_t)(1<<1))
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/** UART Auto baudrate restart */
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#define UART_ACR_AUTO_RESTART ((uint32_t)(1<<2))
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/** UART End of auto-baud interrupt clear */
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#define UART_ACR_ABEOINT_CLR ((uint32_t)(1<<8))
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/** UART Auto-baud time-out interrupt clear */
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#define UART_ACR_ABTOINT_CLR ((uint32_t)(1<<9))
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/** UART Auto Baudrate register bit mask */
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#define UART_ACR_BITMASK ((uint32_t)(0x307))
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/*********************************************************************//**
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* Macro defines for Macro defines for UART IrDA control register
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**********************************************************************/
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/** IrDA mode enable */
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#define UART_ICR_IRDAEN ((uint32_t)(1<<0))
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/** IrDA serial input inverted */
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#define UART_ICR_IRDAINV ((uint32_t)(1<<1))
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/** IrDA fixed pulse width mode */
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#define UART_ICR_FIXPULSE_EN ((uint32_t)(1<<2))
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/** PulseDiv - Configures the pulse when FixPulseEn = 1 */
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#define UART_ICR_PULSEDIV(n) ((uint32_t)((n&0x07)<<3))
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/** UART IRDA bit mask */
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#define UART_ICR_BITMASK ((uint32_t)(0x3F))
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/*********************************************************************//**
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* Macro defines for Macro defines for UART Fractional divider register
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**********************************************************************/
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/** Baud-rate generation pre-scaler divisor */
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#define UART_FDR_DIVADDVAL(n) ((uint32_t)(n&0x0F))
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/** Baud-rate pre-scaler multiplier value */
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#define UART_FDR_MULVAL(n) ((uint32_t)((n<<4)&0xF0))
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/** UART Fractional Divider register bit mask */
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#define UART_FDR_BITMASK ((uint32_t)(0xFF))
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/*********************************************************************//**
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* Macro defines for Macro defines for UART Tx Enable register
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**********************************************************************/
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/** Transmit enable bit */
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#define UART_TER_TXEN ((uint8_t)(1<<7))
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/** UART Transmit Enable Register bit mask */
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#define UART_TER_BITMASK ((uint8_t)(0x80))
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/*********************************************************************//**
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* Macro defines for Macro defines for UART1 RS485 Control register
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**********************************************************************/
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/** RS-485/EIA-485 Normal Multi-drop Mode (NMM) is disabled */
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#define UART1_RS485CTRL_NMM_EN ((uint32_t)(1<<0))
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/** The receiver is disabled */
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#define UART1_RS485CTRL_RX_DIS ((uint32_t)(1<<1))
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/** Auto Address Detect (AAD) is enabled */
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#define UART1_RS485CTRL_AADEN ((uint32_t)(1<<2))
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/** If direction control is enabled (bit DCTRL = 1), pin DTR is used for direction control */
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#define UART1_RS485CTRL_SEL_DTR ((uint32_t)(1<<3))
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/** Enable Auto Direction Control */
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#define UART1_RS485CTRL_DCTRL_EN ((uint32_t)(1<<4))
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/** This bit reverses the polarity of the direction control signal on the RTS (or DTR) pin.
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The direction control pin will be driven to logic "1" when the transmitter has data to be sent */
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#define UART1_RS485CTRL_OINV_1 ((uint32_t)(1<<5))
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/** RS485 control bit-mask value */
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#define UART1_RS485CTRL_BITMASK ((uint32_t)(0x3F))
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/*********************************************************************//**
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* Macro defines for Macro defines for UART1 RS-485 Address Match register
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**********************************************************************/
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#define UART1_RS485ADRMATCH_BITMASK ((uint8_t)(0xFF)) /**< Bit mask value */
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/*********************************************************************//**
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* Macro defines for Macro defines for UART1 RS-485 Delay value register
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**********************************************************************/
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/* Macro defines for UART1 RS-485 Delay value register */
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#define UART1_RS485DLY_BITMASK ((uint8_t)(0xFF)) /** Bit mask value */
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/*********************************************************************//**
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* Macro defines for Macro defines for UART FIFO Level register
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**********************************************************************/
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/** Reflects the current level of the UART receiver FIFO */
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#define UART_FIFOLVL_RXFIFOLVL(n) ((uint32_t)(n&0x0F))
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/** Reflects the current level of the UART transmitter FIFO */
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#define UART_FIFOLVL_TXFIFOLVL(n) ((uint32_t)((n>>8)&0x0F))
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/** UART FIFO Level Register bit mask */
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#define UART_FIFOLVL_BITMASK ((uint32_t)(0x0F0F))
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/**
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* @}
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*/
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/* Public Types --------------------------------------------------------------- */
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/** @defgroup UART_Public_Types UART Public Types
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* @{
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*/
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/**
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* @brief UART Databit type definitions
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*/
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typedef enum {
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UART_DATABIT_5 = 0, /*!< UART 5 bit data mode */
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UART_DATABIT_6, /*!< UART 6 bit data mode */
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UART_DATABIT_7, /*!< UART 7 bit data mode */
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UART_DATABIT_8 /*!< UART 8 bit data mode */
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} UART_DATABIT_Type;
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/**
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* @brief UART Stop bit type definitions
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*/
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typedef enum {
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UART_STOPBIT_1 = (0), /*!< UART 1 Stop Bits Select */
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UART_STOPBIT_2, /*!< UART Two Stop Bits Select */
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} UART_STOPBIT_Type;
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/**
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* @brief UART Parity type definitions
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*/
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typedef enum {
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UART_PARITY_NONE = 0, /*!< No parity */
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UART_PARITY_ODD, /*!< Odd parity */
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UART_PARITY_EVEN, /*!< Even parity */
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UART_PARITY_SP_1, /*!< Forced "1" stick parity */
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UART_PARITY_SP_0 /*!< Forced "0" stick parity */
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} UART_PARITY_Type;
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/**
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* @brief FIFO Level type definitions
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*/
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typedef enum {
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UART_FIFO_TRGLEV0 = 0, /*!< UART FIFO trigger level 0: 1 character */
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UART_FIFO_TRGLEV1, /*!< UART FIFO trigger level 1: 4 character */
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UART_FIFO_TRGLEV2, /*!< UART FIFO trigger level 2: 8 character */
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UART_FIFO_TRGLEV3 /*!< UART FIFO trigger level 3: 14 character */
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} UART_FITO_LEVEL_Type;
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/********************************************************************//**
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* @brief UART Interrupt Type definitions
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**********************************************************************/
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typedef enum {
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UART_INTCFG_RBR = 0, /*!< RBR Interrupt enable*/
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UART_INTCFG_THRE, /*!< THR Interrupt enable*/
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UART_INTCFG_RLS, /*!< RX line status interrupt enable*/
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UART1_INTCFG_MS, /*!< Modem status interrupt enable (UART1 only) */
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UART1_INTCFG_CTS, /*!< CTS1 signal transition interrupt enable (UART1 only) */
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UART_INTCFG_ABEO, /*!< Enables the end of auto-baud interrupt */
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UART_INTCFG_ABTO /*!< Enables the auto-baud time-out interrupt */
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} UART_INT_Type;
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/**
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* @brief UART Line Status Type definition
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*/
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typedef enum {
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UART_LINESTAT_RDR = UART_LSR_RDR, /*!<Line status register: Receive data ready*/
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UART_LINESTAT_OE = UART_LSR_OE, /*!<Line status register: Overrun error*/
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UART_LINESTAT_PE = UART_LSR_PE, /*!<Line status register: Parity error*/
|
|
UART_LINESTAT_FE = UART_LSR_FE, /*!<Line status register: Framing error*/
|
|
UART_LINESTAT_BI = UART_LSR_BI, /*!<Line status register: Break interrupt*/
|
|
UART_LINESTAT_THRE = UART_LSR_THRE, /*!<Line status register: Transmit holding register empty*/
|
|
UART_LINESTAT_TEMT = UART_LSR_TEMT, /*!<Line status register: Transmitter empty*/
|
|
UART_LINESTAT_RXFE = UART_LSR_RXFE /*!<Error in RX FIFO*/
|
|
} UART_LS_Type;
|
|
|
|
/**
|
|
* @brief UART Auto-baudrate mode type definition
|
|
*/
|
|
typedef enum {
|
|
UART_AUTOBAUD_MODE0 = 0, /**< UART Auto baudrate Mode 0 */
|
|
UART_AUTOBAUD_MODE1, /**< UART Auto baudrate Mode 1 */
|
|
} UART_AB_MODE_Type;
|
|
|
|
/**
|
|
* @brief Auto Baudrate mode configuration type definition
|
|
*/
|
|
typedef struct {
|
|
UART_AB_MODE_Type ABMode; /**< Autobaudrate mode */
|
|
FunctionalState AutoRestart; /**< Auto Restart state */
|
|
} UART_AB_CFG_Type;
|
|
|
|
/**
|
|
* @brief UART End of Auto-baudrate type definition
|
|
*/
|
|
typedef enum {
|
|
UART_AUTOBAUD_INTSTAT_ABEO = UART_IIR_ABEO_INT, /**< UART End of auto-baud interrupt */
|
|
UART_AUTOBAUD_INTSTAT_ABTO = UART_IIR_ABTO_INT /**< UART Auto-baud time-out interrupt */
|
|
}UART_ABEO_Type;
|
|
|
|
/**
|
|
* UART IrDA Control type Definition
|
|
*/
|
|
typedef enum
|
|
{
|
|
/** Pulse width = 2 * Tpclk
|
|
- Configures the pulse when FixPulseEn = 1 */
|
|
UART_IrDA_PULSEDIV2 = 0,
|
|
|
|
/** Pulse width = 4 * Tpclk
|
|
- Configures the pulse when FixPulseEn = 1 */
|
|
UART_IrDA_PULSEDIV4,
|
|
|
|
/** Pulse width = 8 * Tpclk
|
|
- Configures the pulse when FixPulseEn = 1 */
|
|
UART_IrDA_PULSEDIV8,
|
|
|
|
/** Pulse width = 16 * Tpclk
|
|
- Configures the pulse when FixPulseEn = 1 */
|
|
UART_IrDA_PULSEDIV16,
|
|
|
|
/** Pulse width = 32 * Tpclk
|
|
- Configures the pulse when FixPulseEn = 1 */
|
|
UART_IrDA_PULSEDIV32,
|
|
|
|
/**< Pulse width = 64 * Tpclk
|
|
- Configures the pulse when FixPulseEn = 1 */
|
|
UART_IrDA_PULSEDIV64,
|
|
|
|
/**< Pulse width = 128 * Tpclk
|
|
- Configures the pulse when FixPulseEn = 1 */
|
|
UART_IrDA_PULSEDIV128,
|
|
|
|
/**< Pulse width = 256 * Tpclk
|
|
- Configures the pulse when FixPulseEn = 1 */
|
|
UART_IrDA_PULSEDIV256
|
|
} UART_IrDA_PULSE_Type;
|
|
|
|
/********************************************************************//**
|
|
* @brief UART1 Full modem - Signal states definition
|
|
**********************************************************************/
|
|
typedef enum {
|
|
INACTIVE = 0, /* In-active state */
|
|
ACTIVE = !INACTIVE /* Active state */
|
|
}UART1_SignalState;
|
|
|
|
/**
|
|
* @brief UART modem status type definition
|
|
*/
|
|
typedef enum {
|
|
UART1_MODEM_STAT_DELTA_CTS = UART1_MSR_DELTA_CTS, /*!< Set upon state change of input CTS */
|
|
UART1_MODEM_STAT_DELTA_DSR = UART1_MSR_DELTA_DSR, /*!< Set upon state change of input DSR */
|
|
UART1_MODEM_STAT_LO2HI_RI = UART1_MSR_LO2HI_RI, /*!< Set upon low to high transition of input RI */
|
|
UART1_MODEM_STAT_DELTA_DCD = UART1_MSR_DELTA_DCD, /*!< Set upon state change of input DCD */
|
|
UART1_MODEM_STAT_CTS = UART1_MSR_CTS, /*!< Clear To Send State */
|
|
UART1_MODEM_STAT_DSR = UART1_MSR_DSR, /*!< Data Set Ready State */
|
|
UART1_MODEM_STAT_RI = UART1_MSR_RI, /*!< Ring Indicator State */
|
|
UART1_MODEM_STAT_DCD = UART1_MSR_DCD /*!< Data Carrier Detect State */
|
|
} UART_MODEM_STAT_type;
|
|
|
|
/**
|
|
* @brief Modem output pin type definition
|
|
*/
|
|
typedef enum {
|
|
UART1_MODEM_PIN_DTR = 0, /*!< Source for modem output pin DTR */
|
|
UART1_MODEM_PIN_RTS /*!< Source for modem output pin RTS */
|
|
} UART_MODEM_PIN_Type;
|
|
|
|
/**
|
|
* @brief UART Modem mode type definition
|
|
*/
|
|
typedef enum {
|
|
UART1_MODEM_MODE_LOOPBACK = 0, /*!< Loop back mode select */
|
|
UART1_MODEM_MODE_AUTO_RTS, /*!< Enable Auto RTS flow-control */
|
|
UART1_MODEM_MODE_AUTO_CTS /*!< Enable Auto CTS flow-control */
|
|
} UART_MODEM_MODE_Type;
|
|
|
|
/**
|
|
* @brief UART Direction Control Pin type definition
|
|
*/
|
|
typedef enum {
|
|
UART1_RS485_DIRCTRL_RTS = 0, /**< Pin RTS is used for direction control */
|
|
UART1_RS485_DIRCTRL_DTR /**< Pin DTR is used for direction control */
|
|
} UART_RS485_DIRCTRL_PIN_Type;
|
|
|
|
/********************************************************************//**
|
|
* @brief UART Configuration Structure definition
|
|
**********************************************************************/
|
|
typedef struct {
|
|
uint32_t Baud_rate; /**< UART baud rate */
|
|
UART_PARITY_Type Parity; /**< Parity selection, should be:
|
|
- UART_PARITY_NONE: No parity
|
|
- UART_PARITY_ODD: Odd parity
|
|
- UART_PARITY_EVEN: Even parity
|
|
- UART_PARITY_SP_1: Forced "1" stick parity
|
|
- UART_PARITY_SP_0: Forced "0" stick parity
|
|
*/
|
|
UART_DATABIT_Type Databits; /**< Number of data bits, should be:
|
|
- UART_DATABIT_5: UART 5 bit data mode
|
|
- UART_DATABIT_6: UART 6 bit data mode
|
|
- UART_DATABIT_7: UART 7 bit data mode
|
|
- UART_DATABIT_8: UART 8 bit data mode
|
|
*/
|
|
UART_STOPBIT_Type Stopbits; /**< Number of stop bits, should be:
|
|
- UART_STOPBIT_1: UART 1 Stop Bits Select
|
|
- UART_STOPBIT_2: UART 2 Stop Bits Select
|
|
*/
|
|
} UART_CFG_Type;
|
|
|
|
/********************************************************************//**
|
|
* @brief UART FIFO Configuration Structure definition
|
|
**********************************************************************/
|
|
|
|
typedef struct {
|
|
FunctionalState FIFO_ResetRxBuf; /**< Reset Rx FIFO command state , should be:
|
|
- ENABLE: Reset Rx FIFO in UART
|
|
- DISABLE: Do not reset Rx FIFO in UART
|
|
*/
|
|
FunctionalState FIFO_ResetTxBuf; /**< Reset Tx FIFO command state , should be:
|
|
- ENABLE: Reset Tx FIFO in UART
|
|
- DISABLE: Do not reset Tx FIFO in UART
|
|
*/
|
|
FunctionalState FIFO_DMAMode; /**< DMA mode, should be:
|
|
- ENABLE: Enable DMA mode in UART
|
|
- DISABLE: Disable DMA mode in UART
|
|
*/
|
|
UART_FITO_LEVEL_Type FIFO_Level; /**< Rx FIFO trigger level, should be:
|
|
- UART_FIFO_TRGLEV0: UART FIFO trigger level 0: 1 character
|
|
- UART_FIFO_TRGLEV1: UART FIFO trigger level 1: 4 character
|
|
- UART_FIFO_TRGLEV2: UART FIFO trigger level 2: 8 character
|
|
- UART_FIFO_TRGLEV3: UART FIFO trigger level 3: 14 character
|
|
*/
|
|
} UART_FIFO_CFG_Type;
|
|
|
|
/********************************************************************//**
|
|
* @brief UART1 Full modem - RS485 Control configuration type
|
|
**********************************************************************/
|
|
typedef struct {
|
|
FunctionalState NormalMultiDropMode_State; /*!< Normal MultiDrop mode State:
|
|
- ENABLE: Enable this function.
|
|
- DISABLE: Disable this function. */
|
|
FunctionalState Rx_State; /*!< Receiver State:
|
|
- ENABLE: Enable Receiver.
|
|
- DISABLE: Disable Receiver. */
|
|
FunctionalState AutoAddrDetect_State; /*!< Auto Address Detect mode state:
|
|
- ENABLE: ENABLE this function.
|
|
- DISABLE: Disable this function. */
|
|
FunctionalState AutoDirCtrl_State; /*!< Auto Direction Control State:
|
|
- ENABLE: Enable this function.
|
|
- DISABLE: Disable this function. */
|
|
UART_RS485_DIRCTRL_PIN_Type DirCtrlPin; /*!< If direction control is enabled, state:
|
|
- UART1_RS485_DIRCTRL_RTS:
|
|
pin RTS is used for direction control.
|
|
- UART1_RS485_DIRCTRL_DTR:
|
|
pin DTR is used for direction control. */
|
|
SetState DirCtrlPol_Level; /*!< Polarity of the direction control signal on
|
|
the RTS (or DTR) pin:
|
|
- RESET: The direction control pin will be driven
|
|
to logic "0" when the transmitter has data to be sent.
|
|
- SET: The direction control pin will be driven
|
|
to logic "1" when the transmitter has data to be sent. */
|
|
uint8_t MatchAddrValue; /*!< address match value for RS-485/EIA-485 mode, 8-bit long */
|
|
uint8_t DelayValue; /*!< delay time is in periods of the baud clock, 8-bit long */
|
|
} UART1_RS485_CTRLCFG_Type;
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
|
|
/* Public Functions ----------------------------------------------------------- */
|
|
/** @defgroup UART_Public_Functions UART Public Functions
|
|
* @{
|
|
*/
|
|
/* UART Init/DeInit functions --------------------------------------------------*/
|
|
void UART_Init(LPC_UART_TypeDef *UARTx, UART_CFG_Type *UART_ConfigStruct);
|
|
void UART_DeInit(LPC_UART_TypeDef* UARTx);
|
|
void UART_ConfigStructInit(UART_CFG_Type *UART_InitStruct);
|
|
|
|
/* UART Send/Receive functions -------------------------------------------------*/
|
|
void UART_SendByte(LPC_UART_TypeDef* UARTx, uint8_t Data);
|
|
uint8_t UART_ReceiveByte(LPC_UART_TypeDef* UARTx);
|
|
uint32_t UART_Send(LPC_UART_TypeDef *UARTx, uint8_t *txbuf,
|
|
uint32_t buflen, TRANSFER_BLOCK_Type flag);
|
|
uint32_t UART_Receive(LPC_UART_TypeDef *UARTx, uint8_t *rxbuf, \
|
|
uint32_t buflen, TRANSFER_BLOCK_Type flag);
|
|
|
|
/* UART FIFO functions ----------------------------------------------------------*/
|
|
void UART_FIFOConfig(LPC_UART_TypeDef *UARTx, UART_FIFO_CFG_Type *FIFOCfg);
|
|
void UART_FIFOConfigStructInit(UART_FIFO_CFG_Type *UART_FIFOInitStruct);
|
|
|
|
/* UART get information functions -----------------------------------------------*/
|
|
uint32_t UART_GetIntId(LPC_UART_TypeDef* UARTx);
|
|
uint8_t UART_GetLineStatus(LPC_UART_TypeDef* UARTx);
|
|
|
|
/* UART operate functions -------------------------------------------------------*/
|
|
void UART_IntConfig(LPC_UART_TypeDef *UARTx, UART_INT_Type UARTIntCfg, \
|
|
FunctionalState NewState);
|
|
void UART_TxCmd(LPC_UART_TypeDef *UARTx, FunctionalState NewState);
|
|
FlagStatus UART_CheckBusy(LPC_UART_TypeDef *UARTx);
|
|
void UART_ForceBreak(LPC_UART_TypeDef* UARTx);
|
|
|
|
/* UART Auto-baud functions -----------------------------------------------------*/
|
|
void UART_ABClearIntPending(LPC_UART_TypeDef *UARTx, UART_ABEO_Type ABIntType);
|
|
void UART_ABCmd(LPC_UART_TypeDef *UARTx, UART_AB_CFG_Type *ABConfigStruct, \
|
|
FunctionalState NewState);
|
|
|
|
/* UART1 FullModem functions ----------------------------------------------------*/
|
|
void UART_FullModemForcePinState(LPC_UART1_TypeDef *UARTx, UART_MODEM_PIN_Type Pin, \
|
|
UART1_SignalState NewState);
|
|
void UART_FullModemConfigMode(LPC_UART1_TypeDef *UARTx, UART_MODEM_MODE_Type Mode, \
|
|
FunctionalState NewState);
|
|
uint8_t UART_FullModemGetStatus(LPC_UART1_TypeDef *UARTx);
|
|
|
|
/* UART RS485 functions ----------------------------------------------------------*/
|
|
void UART_RS485Config(LPC_UART_TypeDef *UARTx,
|
|
UART1_RS485_CTRLCFG_Type *RS485ConfigStruct);
|
|
void UART_RS485ReceiverCmd(LPC_UART_TypeDef *UARTx, FunctionalState NewState);
|
|
void UART_RS485SendSlvAddr(LPC_UART_TypeDef *UARTx, uint8_t SlvAddr);
|
|
uint32_t UART_RS485SendData(LPC_UART_TypeDef *UARTx, uint8_t *pData, uint32_t size);
|
|
|
|
/* UART IrDA functions-------------------------------------------------------------*/
|
|
void UART_IrDAInvtInputCmd(LPC_UART_TypeDef* UARTx, FunctionalState NewState);
|
|
void UART_IrDACmd(LPC_UART_TypeDef* UARTx, FunctionalState NewState);
|
|
void UART_IrDAPulseDivConfig(LPC_UART_TypeDef *UARTx, UART_IrDA_PULSE_Type PulseDiv);
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
|
|
|
|
#endif /* __LPC177X_8X_UART_H_ */
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/* --------------------------------- End Of File ------------------------------ */
|