mirror of
https://github.com/RT-Thread/rt-thread.git
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943f83d58f
1. Add "drv_eth.c" for all imxrt platforms. 2. Add ksz8081 phy driver for imxrt1052-nxp-evk board. 3. Disable the LED demo in main.c file if enable the ENET and ksz8081 phy, because the PINs of LED and ksz8081 reset are from the same GPIO. 4. Update the relevant Kconfig and Sconscript files. Signed-off-by: Gavin Liu <gavin-liugang@outlook.com>
470 lines
22 KiB
C
470 lines
22 KiB
C
/*
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* Copyright (c) 2006-2018, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2009-01-05 Bernard first implementation
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*/
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#include <rthw.h>
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#include <rtthread.h>
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#include "board.h"
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#include "pin_mux.h"
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#include "fsl_iomuxc.h"
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#include "fsl_gpio.h"
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#ifdef BSP_USING_DMA
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#include "fsl_dmamux.h"
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#include "fsl_edma.h"
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#endif
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#define NVIC_PRIORITYGROUP_0 0x00000007U /*!< 0 bits for pre-emption priority
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4 bits for subpriority */
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#define NVIC_PRIORITYGROUP_1 0x00000006U /*!< 1 bits for pre-emption priority
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3 bits for subpriority */
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#define NVIC_PRIORITYGROUP_2 0x00000005U /*!< 2 bits for pre-emption priority
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2 bits for subpriority */
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#define NVIC_PRIORITYGROUP_3 0x00000004U /*!< 3 bits for pre-emption priority
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1 bits for subpriority */
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#define NVIC_PRIORITYGROUP_4 0x00000003U /*!< 4 bits for pre-emption priority
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0 bits for subpriority */
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/* MPU configuration. */
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static void BOARD_ConfigMPU(void)
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{
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/* Disable I cache and D cache */
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SCB_DisableICache();
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SCB_DisableDCache();
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/* Disable MPU */
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ARM_MPU_Disable();
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/* Region 0 setting */
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MPU->RBAR = ARM_MPU_RBAR(0, 0xC0000000U);
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MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB);
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/* Region 1 setting */
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MPU->RBAR = ARM_MPU_RBAR(1, 0x80000000U);
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MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB);
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/* Region 2 setting */
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// spi flash: normal type, cacheable, no bufferable, no shareable
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MPU->RBAR = ARM_MPU_RBAR(2, 0x60000000U);
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MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 0, 0, ARM_MPU_REGION_SIZE_512MB);
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/* Region 3 setting */
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MPU->RBAR = ARM_MPU_RBAR(3, 0x00000000U);
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MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB);
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/* Region 4 setting */
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MPU->RBAR = ARM_MPU_RBAR(4, 0x00000000U);
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MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128KB);
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/* Region 5 setting */
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MPU->RBAR = ARM_MPU_RBAR(5, 0x20000000U);
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MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128KB);
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/* Region 6 setting */
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MPU->RBAR = ARM_MPU_RBAR(6, 0x20200000U);
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MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_256KB);
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#if defined(BSP_USING_SDRAM)
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/* Region 7 setting */
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MPU->RBAR = ARM_MPU_RBAR(7, 0x80000000U);
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MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_32MB);
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/* Region 8 setting */
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MPU->RBAR = ARM_MPU_RBAR(8, 0x81E00000U);
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MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 1, 1, 0, 0, 0, ARM_MPU_REGION_SIZE_2MB);
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#endif
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/* Enable MPU */
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ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk);
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/* Enable I cache and D cache */
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SCB_EnableDCache();
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SCB_EnableICache();
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}
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/* This is the timer interrupt service routine. */
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void SysTick_Handler(void)
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{
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/* enter interrupt */
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rt_interrupt_enter();
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rt_tick_increase();
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/* leave interrupt */
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rt_interrupt_leave();
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}
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#ifdef BSP_USING_DMA
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void imxrt_dma_init(void)
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{
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edma_config_t config;
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DMAMUX_Init(DMAMUX);
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EDMA_GetDefaultConfig(&config);
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EDMA_Init(DMA0, &config);
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}
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#endif
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#ifdef BSP_USING_LPUART
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void imxrt_uart_pins_init(void)
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{
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#ifdef BSP_USING_LPUART1
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IOMUXC_SetPinMux(
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IOMUXC_GPIO_AD_B0_12_LPUART1_TX, /* GPIO_AD_B0_12 is configured as LPUART1_TX */
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0U); /* Software Input On Field: Input Path is determined by functionality */
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IOMUXC_SetPinMux(
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IOMUXC_GPIO_AD_B0_13_LPUART1_RX, /* GPIO_AD_B0_13 is configured as LPUART1_RX */
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0U); /* Software Input On Field: Input Path is determined by functionality */
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IOMUXC_SetPinConfig(
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IOMUXC_GPIO_AD_B0_12_LPUART1_TX, /* GPIO_AD_B0_12 PAD functional properties : */
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0x10B0u); /* Slew Rate Field: Slow Slew Rate
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Drive Strength Field: R0/6
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Speed Field: medium(100MHz)
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Open Drain Enable Field: Open Drain Disabled
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Pull / Keep Enable Field: Pull/Keeper Enabled
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Pull / Keep Select Field: Keeper
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Pull Up / Down Config. Field: 100K Ohm Pull Down
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Hyst. Enable Field: Hysteresis Disabled */
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IOMUXC_SetPinConfig(
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IOMUXC_GPIO_AD_B0_13_LPUART1_RX, /* GPIO_AD_B0_13 PAD functional properties : */
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0x10B0u); /* Slew Rate Field: Slow Slew Rate
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Drive Strength Field: R0/6
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Speed Field: medium(100MHz)
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Open Drain Enable Field: Open Drain Disabled
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Pull / Keep Enable Field: Pull/Keeper Enabled
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Pull / Keep Select Field: Keeper
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Pull Up / Down Config. Field: 100K Ohm Pull Down
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Hyst. Enable Field: Hysteresis Disabled */
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#endif
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#ifdef BSP_USING_LPUART2
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IOMUXC_SetPinMux(
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IOMUXC_GPIO_AD_B1_02_LPUART2_TX,
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0U);
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IOMUXC_SetPinMux(
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IOMUXC_GPIO_AD_B1_03_LPUART2_RX,
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0U);
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IOMUXC_SetPinConfig(
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IOMUXC_GPIO_AD_B1_02_LPUART2_TX,
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0x10B0u);
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IOMUXC_SetPinConfig(
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IOMUXC_GPIO_AD_B1_03_LPUART2_RX,
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0x10B0u);
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#endif
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#ifdef BSP_USING_LPUART3
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IOMUXC_SetPinMux(
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IOMUXC_GPIO_AD_B1_06_LPUART3_TX,
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0U);
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IOMUXC_SetPinMux(
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IOMUXC_GPIO_AD_B1_07_LPUART3_RX,
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0U);
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IOMUXC_SetPinConfig(
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IOMUXC_GPIO_AD_B1_06_LPUART3_TX,
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0x10B0u);
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IOMUXC_SetPinConfig(
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IOMUXC_GPIO_AD_B1_07_LPUART3_RX,
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0x10B0u);
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#endif
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#ifdef BSP_USING_LPUART4
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IOMUXC_SetPinMux(
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IOMUXC_GPIO_B1_00_LPUART4_TX,
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0U);
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IOMUXC_SetPinMux(
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IOMUXC_GPIO_B1_01_LPUART4_RX,
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0U);
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IOMUXC_SetPinConfig(
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IOMUXC_GPIO_B1_00_LPUART4_TX,
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0x10B0u);
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IOMUXC_SetPinConfig(
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IOMUXC_GPIO_B1_01_LPUART4_RX,
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0x10B0u);
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#endif
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#ifdef BSP_USING_LPUART5
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IOMUXC_SetPinMux(
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IOMUXC_GPIO_B1_12_LPUART5_TX,
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0U);
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IOMUXC_SetPinMux(
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IOMUXC_GPIO_B1_13_LPUART5_RX,
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0U);
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IOMUXC_SetPinConfig(
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IOMUXC_GPIO_B1_12_LPUART5_TX,
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0x10B0u);
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IOMUXC_SetPinConfig(
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IOMUXC_GPIO_B1_13_LPUART5_RX,
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0x10B0u);
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#endif
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#ifdef BSP_USING_LPUART6
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IOMUXC_SetPinMux(
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IOMUXC_GPIO_AD_B0_02_LPUART6_TX,
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0U);
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IOMUXC_SetPinMux(
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IOMUXC_GPIO_AD_B0_03_LPUART6_RX,
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0U);
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IOMUXC_SetPinConfig(
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IOMUXC_GPIO_AD_B0_02_LPUART6_TX,
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0x10B0u);
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IOMUXC_SetPinConfig(
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IOMUXC_GPIO_AD_B0_03_LPUART6_RX,
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0x10B0u);
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#endif
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#ifdef BSP_USING_LPUART7
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IOMUXC_SetPinMux(
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IOMUXC_GPIO_EMC_31_LPUART7_TX,
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0U);
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IOMUXC_SetPinMux(
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IOMUXC_GPIO_EMC_32_LPUART7_RX,
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0U);
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IOMUXC_SetPinConfig(
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IOMUXC_GPIO_EMC_31_LPUART7_TX,
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0x10B0u);
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IOMUXC_SetPinConfig(
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IOMUXC_GPIO_EMC_32_LPUART7_RX,
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0x10B0u);
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#endif
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#ifdef BSP_USING_LPUART8
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IOMUXC_SetPinMux(
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IOMUXC_GPIO_AD_B1_10_LPUART8_TX,
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0U);
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IOMUXC_SetPinMux(
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IOMUXC_GPIO_AD_B1_11_LPUART8_RX,
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0U);
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IOMUXC_SetPinConfig(
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IOMUXC_GPIO_AD_B1_10_LPUART8_TX,
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0x10B0u);
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IOMUXC_SetPinConfig(
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IOMUXC_GPIO_AD_B1_11_LPUART8_RX,
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0x10B0u);
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#endif
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}
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#endif /* BSP_USING_LPUART */
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#ifdef BSP_USING_ETH
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void imxrt_enet_pins_init(void)
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{
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CLOCK_EnableClock(kCLOCK_Iomuxc); /* iomuxc clock (iomuxc_clk_enable): 0x03u */
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IOMUXC_SetPinMux(
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IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, /* GPIO_AD_B0_09 is configured as GPIO1_IO09 */
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0U); /* Software Input On Field: Input Path is determined by functionality */
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IOMUXC_SetPinMux(
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IOMUXC_GPIO_AD_B0_10_GPIO1_IO10, /* GPIO_AD_B0_10 is configured as GPIO1_IO10 */
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0U);
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IOMUXC_SetPinMux(
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IOMUXC_GPIO_B1_04_ENET_RX_DATA00, /* GPIO_B1_04 is configured as ENET_RX_DATA00 */
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0U); /* Software Input On Field: Input Path is determined by functionality */
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IOMUXC_SetPinMux(
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IOMUXC_GPIO_B1_05_ENET_RX_DATA01, /* GPIO_B1_05 is configured as ENET_RX_DATA01 */
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0U); /* Software Input On Field: Input Path is determined by functionality */
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IOMUXC_SetPinMux(
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IOMUXC_GPIO_B1_06_ENET_RX_EN, /* GPIO_B1_06 is configured as ENET_RX_EN */
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0U); /* Software Input On Field: Input Path is determined by functionality */
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IOMUXC_SetPinMux(
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IOMUXC_GPIO_B1_07_ENET_TX_DATA00, /* GPIO_B1_07 is configured as ENET_TX_DATA00 */
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0U); /* Software Input On Field: Input Path is determined by functionality */
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IOMUXC_SetPinMux(
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IOMUXC_GPIO_B1_08_ENET_TX_DATA01, /* GPIO_B1_08 is configured as ENET_TX_DATA01 */
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0U); /* Software Input On Field: Input Path is determined by functionality */
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IOMUXC_SetPinMux(
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IOMUXC_GPIO_B1_09_ENET_TX_EN, /* GPIO_B1_09 is configured as ENET_TX_EN */
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0U); /* Software Input On Field: Input Path is determined by functionality */
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IOMUXC_SetPinMux(
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IOMUXC_GPIO_B1_10_ENET_REF_CLK, /* GPIO_B1_10 is configured as ENET_REF_CLK */
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1U); /* Software Input On Field: Force input path of pad GPIO_B1_10 */
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IOMUXC_SetPinMux(
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IOMUXC_GPIO_B1_11_ENET_RX_ER, /* GPIO_B1_11 is configured as ENET_RX_ER */
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0U); /* Software Input On Field: Input Path is determined by functionality */
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IOMUXC_SetPinMux(
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IOMUXC_GPIO_EMC_40_ENET_MDC, /* GPIO_EMC_40 is configured as ENET_MDC */
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0U); /* Software Input On Field: Input Path is determined by functionality */
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IOMUXC_SetPinMux(
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IOMUXC_GPIO_EMC_41_ENET_MDIO, /* GPIO_EMC_41 is configured as ENET_MDIO */
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0U); /* Software Input On Field: Input Path is determined by functionality */
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IOMUXC_SetPinConfig(
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IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, /* GPIO_AD_B0_09 PAD functional properties : */
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0xB0A9u); /* Slew Rate Field: Fast Slew Rate
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Drive Strength Field: R0/5
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Speed Field: medium(100MHz)
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Open Drain Enable Field: Open Drain Disabled
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Pull / Keep Enable Field: Pull/Keeper Enabled
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Pull / Keep Select Field: Pull
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Pull Up / Down Config. Field: 100K Ohm Pull Up
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Hyst. Enable Field: Hysteresis Disabled */
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IOMUXC_SetPinConfig(
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IOMUXC_GPIO_AD_B0_10_GPIO1_IO10, /* GPIO_AD_B0_10 PAD functional properties : */
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0xB0A9u); /* Slew Rate Field: Fast Slew Rate
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Drive Strength Field: R0/5
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Speed Field: medium(100MHz)
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Open Drain Enable Field: Open Drain Disabled
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Pull / Keep Enable Field: Pull/Keeper Enabled
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Pull / Keep Select Field: Pull
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Pull Up / Down Config. Field: 100K Ohm Pull Up
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Hyst. Enable Field: Hysteresis Disabled */
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IOMUXC_SetPinConfig(
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IOMUXC_GPIO_B1_04_ENET_RX_DATA00, /* GPIO_B1_04 PAD functional properties : */
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0xB0E9u); /* Slew Rate Field: Fast Slew Rate
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Drive Strength Field: R0/5
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Speed Field: max(200MHz)
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Open Drain Enable Field: Open Drain Disabled
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Pull / Keep Enable Field: Pull/Keeper Enabled
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Pull / Keep Select Field: Pull
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Pull Up / Down Config. Field: 100K Ohm Pull Up
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Hyst. Enable Field: Hysteresis Disabled */
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IOMUXC_SetPinConfig(
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IOMUXC_GPIO_B1_05_ENET_RX_DATA01, /* GPIO_B1_05 PAD functional properties : */
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0xB0E9u); /* Slew Rate Field: Fast Slew Rate
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Drive Strength Field: R0/5
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Speed Field: max(200MHz)
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Open Drain Enable Field: Open Drain Disabled
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Pull / Keep Enable Field: Pull/Keeper Enabled
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Pull / Keep Select Field: Pull
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Pull Up / Down Config. Field: 100K Ohm Pull Up
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Hyst. Enable Field: Hysteresis Disabled */
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IOMUXC_SetPinConfig(
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IOMUXC_GPIO_B1_06_ENET_RX_EN, /* GPIO_B1_06 PAD functional properties : */
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0xB0E9u); /* Slew Rate Field: Fast Slew Rate
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Drive Strength Field: R0/5
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Speed Field: max(200MHz)
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Open Drain Enable Field: Open Drain Disabled
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Pull / Keep Enable Field: Pull/Keeper Enabled
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Pull / Keep Select Field: Pull
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Pull Up / Down Config. Field: 100K Ohm Pull Up
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Hyst. Enable Field: Hysteresis Disabled */
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IOMUXC_SetPinConfig(
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IOMUXC_GPIO_B1_07_ENET_TX_DATA00, /* GPIO_B1_07 PAD functional properties : */
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0xB0E9u); /* Slew Rate Field: Fast Slew Rate
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Drive Strength Field: R0/5
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Speed Field: max(200MHz)
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Open Drain Enable Field: Open Drain Disabled
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Pull / Keep Enable Field: Pull/Keeper Enabled
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Pull / Keep Select Field: Pull
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Pull Up / Down Config. Field: 100K Ohm Pull Up
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Hyst. Enable Field: Hysteresis Disabled */
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IOMUXC_SetPinConfig(
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IOMUXC_GPIO_B1_08_ENET_TX_DATA01, /* GPIO_B1_08 PAD functional properties : */
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0xB0E9u); /* Slew Rate Field: Fast Slew Rate
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Drive Strength Field: R0/5
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Speed Field: max(200MHz)
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Open Drain Enable Field: Open Drain Disabled
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Pull / Keep Enable Field: Pull/Keeper Enabled
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Pull / Keep Select Field: Pull
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Pull Up / Down Config. Field: 100K Ohm Pull Up
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Hyst. Enable Field: Hysteresis Disabled */
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IOMUXC_SetPinConfig(
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IOMUXC_GPIO_B1_09_ENET_TX_EN, /* GPIO_B1_09 PAD functional properties : */
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0xB0E9u); /* Slew Rate Field: Fast Slew Rate
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Drive Strength Field: R0/5
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Speed Field: max(200MHz)
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Open Drain Enable Field: Open Drain Disabled
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Pull / Keep Enable Field: Pull/Keeper Enabled
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Pull / Keep Select Field: Pull
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Pull Up / Down Config. Field: 100K Ohm Pull Up
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Hyst. Enable Field: Hysteresis Disabled */
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IOMUXC_SetPinConfig(
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IOMUXC_GPIO_B1_10_ENET_REF_CLK, /* GPIO_B1_10 PAD functional properties : */
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0x31u); /* Slew Rate Field: Fast Slew Rate
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Drive Strength Field: R0/6
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Speed Field: low(50MHz)
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Open Drain Enable Field: Open Drain Disabled
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Pull / Keep Enable Field: Pull/Keeper Disabled
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Pull / Keep Select Field: Keeper
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Pull Up / Down Config. Field: 100K Ohm Pull Down
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Hyst. Enable Field: Hysteresis Disabled */
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IOMUXC_SetPinConfig(
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IOMUXC_GPIO_B1_11_ENET_RX_ER, /* GPIO_B1_11 PAD functional properties : */
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0xB0E9u); /* Slew Rate Field: Fast Slew Rate
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Drive Strength Field: R0/5
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Speed Field: max(200MHz)
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Open Drain Enable Field: Open Drain Disabled
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Pull / Keep Enable Field: Pull/Keeper Enabled
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Pull / Keep Select Field: Pull
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Pull Up / Down Config. Field: 100K Ohm Pull Up
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Hyst. Enable Field: Hysteresis Disabled */
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IOMUXC_SetPinConfig(
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IOMUXC_GPIO_EMC_40_ENET_MDC, /* GPIO_EMC_40 PAD functional properties : */
|
|
0xB0E9u); /* Slew Rate Field: Fast Slew Rate
|
|
Drive Strength Field: R0/5
|
|
Speed Field: max(200MHz)
|
|
Open Drain Enable Field: Open Drain Disabled
|
|
Pull / Keep Enable Field: Pull/Keeper Enabled
|
|
Pull / Keep Select Field: Pull
|
|
Pull Up / Down Config. Field: 100K Ohm Pull Up
|
|
Hyst. Enable Field: Hysteresis Disabled */
|
|
IOMUXC_SetPinConfig(
|
|
IOMUXC_GPIO_EMC_41_ENET_MDIO, /* GPIO_EMC_41 PAD functional properties : */
|
|
0xB829u); /* Slew Rate Field: Fast Slew Rate
|
|
Drive Strength Field: R0/5
|
|
Speed Field: low(50MHz)
|
|
Open Drain Enable Field: Open Drain Enabled
|
|
Pull / Keep Enable Field: Pull/Keeper Enabled
|
|
Pull / Keep Select Field: Pull
|
|
Pull Up / Down Config. Field: 100K Ohm Pull Up
|
|
Hyst. Enable Field: Hysteresis Disabled */
|
|
}
|
|
|
|
void imxrt_enet_phy_reset_by_gpio(void)
|
|
{
|
|
gpio_pin_config_t gpio_config = {kGPIO_DigitalOutput, 0, kGPIO_NoIntmode};
|
|
|
|
GPIO_PinInit(GPIO1, 9, &gpio_config);
|
|
GPIO_PinInit(GPIO1, 10, &gpio_config);
|
|
/* pull up the ENET_INT before RESET. */
|
|
GPIO_WritePinOutput(GPIO1, 10, 1);
|
|
GPIO_WritePinOutput(GPIO1, 9, 0);
|
|
rt_thread_delay(100);
|
|
GPIO_WritePinOutput(GPIO1, 9, 1);
|
|
}
|
|
#endif /* BSP_USING_ETH */
|
|
|
|
/**
|
|
* This function will initial rt1050 board.
|
|
*/
|
|
void rt_hw_board_init()
|
|
{
|
|
BOARD_ConfigMPU();
|
|
BOARD_InitPins();
|
|
BOARD_BootClockRUN();
|
|
|
|
NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
|
|
SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND);
|
|
|
|
#ifdef BSP_USING_LPUART
|
|
imxrt_uart_pins_init();
|
|
#endif
|
|
|
|
#ifdef BSP_USING_ETH
|
|
imxrt_enet_pins_init();
|
|
#endif
|
|
|
|
#ifdef BSP_USING_DMA
|
|
imxrt_dma_init();
|
|
#endif
|
|
|
|
#ifdef RT_USING_HEAP
|
|
rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
|
|
#endif
|
|
|
|
#ifdef RT_USING_COMPONENTS_INIT
|
|
rt_components_board_init();
|
|
#endif
|
|
|
|
#ifdef RT_USING_CONSOLE
|
|
rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
|
|
#endif
|
|
}
|
|
|