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66 lines
1.6 KiB
C
66 lines
1.6 KiB
C
/*
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* Copyright (c) 2006-2020, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2011-09-15 Bernard first version
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*/
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#ifndef __CP15_H__
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#define __CP15_H__
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#ifndef __STATIC_FORCEINLINE
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#define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline
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#endif
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#define __WFI() __asm__ volatile ("wfi":::"memory")
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#define __WFE() __asm__ volatile ("wfe":::"memory")
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#define __SEV() __asm__ volatile ("sev")
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__STATIC_FORCEINLINE void __ISB(void)
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{
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__asm__ volatile ("isb 0xF":::"memory");
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}
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/**
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\brief Data Synchronization Barrier
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\details Acts as a special kind of Data Memory Barrier.
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It completes when all explicit memory accesses before this instruction complete.
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*/
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__STATIC_FORCEINLINE void __DSB(void)
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{
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__asm__ volatile ("dsb 0xF":::"memory");
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}
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/**
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\brief Data Memory Barrier
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\details Ensures the apparent order of the explicit memory operations before
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and after the instruction, without ensuring their completion.
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*/
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__STATIC_FORCEINLINE void __DMB(void)
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{
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__asm__ volatile ("dmb 0xF":::"memory");
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}
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unsigned long rt_cpu_get_smp_id(void);
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void rt_cpu_mmu_disable(void);
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void rt_cpu_mmu_enable(void);
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void rt_cpu_tlb_set(volatile unsigned long*);
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void rt_cpu_dcache_clean_flush(void);
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void rt_cpu_icache_flush(void);
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void rt_cpu_vector_set_base(rt_ubase_t addr);
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void rt_hw_mmu_init(void);
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void rt_hw_vector_init(void);
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void set_timer_counter(unsigned int counter);
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void set_timer_control(unsigned int control);
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#endif
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