378 lines
13 KiB
C
378 lines
13 KiB
C
/*
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* Copyright (C) 2020, Huada Semiconductor Co., Ltd.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2020-10-30 CDT first version
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*/
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#ifndef __DRV_SPI_H__
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#define __DRV_SPI_H__
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/*******************************************************************************
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* Include files
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******************************************************************************/
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#include <rtthread.h>
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#include "rtdevice.h"
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#include "drv_dma.h"
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#include "board_config.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifdef BSP_USING_SPI1
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#define SPI1_BUS_NAME "spi1"
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#define SPI1_BUS_MUTEX_NAME "spi1_bus_mutex"
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#endif
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#ifdef BSP_USING_SPI2
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#define SPI2_BUS_NAME "spi2"
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#define SPI2_BUS_MUTEX_NAME "spi2_bus_mutex"
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#endif
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#ifdef BSP_USING_SPI3
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#define SPI3_BUS_NAME "spi3"
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#define SPI3_BUS_MUTEX_NAME "spi3_bus_mutex"
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#endif
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#ifdef BSP_USING_SPI4
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#define SPI4_BUS_NAME "spi4"
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#define SPI4_BUS_MUTEX_NAME "spi4_bus_mutex"
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#endif
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#ifdef BSP_USING_SPI5
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#define SPI4_BUS_NAME "spi5"
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#define SPI4_BUS_MUTEX_NAME "spi5_bus_mutex"
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#endif
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#ifdef BSP_USING_SPI6
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#define SPI4_BUS_NAME "spi6"
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#define SPI4_BUS_MUTEX_NAME "spi6_bus_mutex"
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#endif
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#ifdef BSP_USING_SPI1
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#ifndef SPI1_BUS_CONFIG
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#define SPI1_BUS_CONFIG \
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{ \
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.Instance = M4_SPI1, \
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.bus_name = SPI1_BUS_NAME, \
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}
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#endif /* SPI1_BUS_CONFIG */
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#endif /* BSP_USING_SPI1 */
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#ifdef BSP_SPI1_TX_USING_DMA
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#ifndef SPI1_TX_DMA_CONFIG
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#define SPI1_TX_DMA_CONFIG \
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{ \
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.Instance = SPI1_TX_DMA_INSTANCE, \
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.channel = SPI1_TX_DMA_CHANNEL, \
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.trigger_evt_src = EVT_SPI1_SPTI, \
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.irq_config = \
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{ \
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.irq = SPI1_TX_DMA_IRQn, \
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.irq_prio = SPI1_TX_DMA_INT_PRIO, \
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.int_src = SPI1_TX_DMA_INT_SRC, \
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} \
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}
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#endif /* SPI1_TX_DMA_CONFIG */
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#endif /* BSP_SPI1_TX_USING_DMA */
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#ifdef BSP_SPI1_RX_USING_DMA
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#ifndef SPI1_RX_DMA_CONFIG
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#define SPI1_RX_DMA_CONFIG \
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{ \
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.Instance = SPI1_RX_DMA_INSTANCE, \
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.channel = SPI1_RX_DMA_CHANNEL, \
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.trigger_evt_src = EVT_SPI1_SPRI, \
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.irq_config = \
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{ \
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.irq = SPI1_RX_DMA_IRQn, \
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.irq_prio = SPI1_RX_DMA_INT_PRIO, \
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.int_src = SPI1_RX_DMA_INT_SRC, \
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} \
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}
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#endif /* SPI1_RX_DMA_CONFIG */
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#endif /* BSP_SPI1_RX_USING_DMA */
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#ifdef BSP_USING_SPI2
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#ifndef SPI2_BUS_CONFIG
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#define SPI2_BUS_CONFIG \
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{ \
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.Instance = M4_SPI2, \
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.bus_name = SPI2_BUS_NAME, \
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}
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#endif /* SPI2_BUS_CONFIG */
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#endif /* BSP_USING_SPI2 */
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#ifdef BSP_SPI2_TX_USING_DMA
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#ifndef SPI2_TX_DMA_CONFIG
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#define SPI2_TX_DMA_CONFIG \
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{ \
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.Instance = SPI2_TX_DMA_INSTANCE, \
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.channel = SPI2_TX_DMA_CHANNEL, \
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.trigger_evt_src = EVT_SPI2_SPTI, \
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.irq_config = \
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{ \
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.irq = SPI2_TX_DMA_IRQn, \
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.irq_prio = SPI2_TX_DMA_INT_PRIO, \
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.int_src = SPI2_TX_DMA_INT_SRC, \
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} \
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}
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#endif /* SPI2_TX_DMA_CONFIG */
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#endif /* BSP_SPI2_TX_USING_DMA */
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#ifdef BSP_SPI2_RX_USING_DMA
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#ifndef SPI2_RX_DMA_CONFIG
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#define SPI2_RX_DMA_CONFIG \
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{ \
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.Instance = SPI2_RX_DMA_INSTANCE, \
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.channel = SPI2_RX_DMA_CHANNEL, \
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.trigger_evt_src = EVT_SPI2_SPRI, \
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.irq_config = \
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{ \
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.irq = SPI2_RX_DMA_IRQn, \
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.irq_prio = SPI2_RX_DMA_INT_PRIO, \
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.int_src = SPI2_RX_DMA_INT_SRC, \
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} \
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}
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#endif /* SPI2_RX_DMA_CONFIG */
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#endif /* BSP_SPI2_RX_USING_DMA */
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#ifdef BSP_USING_SPI3
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#ifndef SPI3_BUS_CONFIG
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#define SPI3_BUS_CONFIG \
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{ \
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.Instance = M4_SPI3, \
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.bus_name = SPI3_BUS_NAME, \
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}
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#endif /* SPI3_BUS_CONFIG */
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#endif /* BSP_USING_SPI3 */
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#ifdef BSP_SPI3_TX_USING_DMA
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#ifndef SPI3_TX_DMA_CONFIG
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#define SPI3_TX_DMA_CONFIG \
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{ \
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.Instance = SPI3_TX_DMA_INSTANCE, \
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.channel = SPI3_TX_DMA_CHANNEL, \
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.trigger_evt_src = EVT_SPI3_SPTI, \
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.irq_config = \
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{ \
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.irq = SPI3_TX_DMA_IRQn, \
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.irq_prio = SPI3_TX_DMA_INT_PRIO, \
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.int_src = SPI3_TX_DMA_INT_SRC, \
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} \
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}
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#endif /* SPI3_TX_DMA_CONFIG */
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#endif /* BSP_SPI3_TX_USING_DMA */
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#ifdef BSP_SPI3_RX_USING_DMA
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#ifndef SPI3_RX_DMA_CONFIG
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#define SPI3_RX_DMA_CONFIG \
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{ \
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.Instance = SPI3_RX_DMA_INSTANCE, \
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.channel = SPI3_RX_DMA_CHANNEL, \
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.trigger_evt_src = EVT_SPI3_SPRI, \
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.irq_config = \
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{ \
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.irq = SPI3_RX_DMA_IRQn, \
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.irq_prio = SPI3_RX_DMA_INT_PRIO, \
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.int_src = SPI3_RX_DMA_INT_SRC, \
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} \
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}
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#endif /* SPI3_RX_DMA_CONFIG */
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#endif /* BSP_SPI3_RX_USING_DMA */
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#ifdef BSP_USING_SPI4
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#ifndef SPI4_BUS_CONFIG
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#define SPI4_BUS_CONFIG \
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{ \
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.Instance = M4_SPI4, \
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.bus_name = SPI4_BUS_NAME, \
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}
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#endif /* SPI4_BUS_CONFIG */
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#endif /* BSP_USING_SPI4 */
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#ifdef BSP_SPI4_TX_USING_DMA
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#ifndef SPI4_TX_DMA_CONFIG
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#define SPI4_TX_DMA_CONFIG \
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{ \
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.Instance = SPI4_TX_DMA_INSTANCE, \
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.channel = SPI4_TX_DMA_CHANNEL, \
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.trigger_evt_src = EVT_SPI4_SPTI, \
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.irq_config = \
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{ \
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.irq = SPI4_TX_DMA_IRQn, \
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.irq_prio = SPI4_TX_DMA_INT_PRIO, \
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.int_src = SPI4_TX_DMA_INT_SRC, \
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} \
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}
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#endif /* SPI4_TX_DMA_CONFIG */
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#endif /* BSP_SPI4_TX_USING_DMA */
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#ifdef BSP_SPI4_RX_USING_DMA
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#ifndef SPI4_RX_DMA_CONFIG
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#define SPI4_RX_DMA_CONFIG \
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{ \
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.Instance = SPI4_RX_DMA_INSTANCE, \
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.channel = SPI4_RX_DMA_CHANNEL, \
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.trigger_evt_src = EVT_SPI4_SPRI, \
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.irq_config = \
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{ \
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.irq = SPI4_RX_DMA_IRQn, \
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.irq_prio = SPI4_RX_DMA_INT_PRIO, \
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.int_src = SPI4_RX_DMA_INT_SRC, \
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} \
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}
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#endif /* SPI4_RX_DMA_CONFIG */
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#endif /* BSP_SPI4_RX_USING_DMA */
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#ifdef BSP_USING_SPI5
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#ifndef SPI5_BUS_CONFIG
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#define SPI5_BUS_CONFIG \
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{ \
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.Instance = M4_SPI5, \
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.bus_name = SPI5_BUS_NAME, \
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}
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#endif /* SPI5_BUS_CONFIG */
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#endif /* BSP_USING_SPI5 */
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#ifdef BSP_SPI5_TX_USING_DMA
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#ifndef SPI5_TX_DMA_CONFIG
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#define SPI5_TX_DMA_CONFIG \
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{ \
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.Instance = SPI5_TX_DMA_INSTANCE, \
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.channel = SPI5_TX_DMA_CHANNEL, \
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.trigger_evt_src = EVT_SPI5_SPTI, \
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.irq_config = \
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{ \
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.irq = SPI5_TX_DMA_IRQn, \
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.irq_prio = SPI5_TX_DMA_INT_PRIO, \
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.int_src = SPI5_TX_DMA_INT_SRC, \
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} \
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}
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#endif /* SPI5_TX_DMA_CONFIG */
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#endif /* BSP_SPI5_TX_USING_DMA */
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#ifdef BSP_SPI5_RX_USING_DMA
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#ifndef SPI5_RX_DMA_CONFIG
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#define SPI5_RX_DMA_CONFIG \
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{ \
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.Instance = SPI5_RX_DMA_INSTANCE, \
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.channel = SPI5_RX_DMA_CHANNEL, \
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.trigger_evt_src = EVT_SPI5_SPRI, \
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.irq_config = \
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{ \
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.irq = SPI5_RX_DMA_IRQn, \
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.irq_prio = SPI5_RX_DMA_INT_PRIO, \
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.int_src = SPI5_RX_DMA_INT_SRC, \
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} \
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}
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#endif /* SPI5_RX_DMA_CONFIG */
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#endif /* BSP_SPI5_RX_USING_DMA */
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#ifdef BSP_USING_SPI6
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#ifndef SPI6_BUS_CONFIG
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#define SPI6_BUS_CONFIG \
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{ \
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.Instance = M4_SPI6, \
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.bus_name = SPI6_BUS_NAME, \
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}
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#endif /* SPI6_BUS_CONFIG */
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#endif /* BSP_USING_SPI6 */
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#ifdef BSP_SPI6_TX_USING_DMA
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#ifndef SPI6_TX_DMA_CONFIG
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#define SPI6_TX_DMA_CONFIG \
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{ \
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.Instance = SPI6_TX_DMA_INSTANCE, \
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.channel = SPI6_TX_DMA_CHANNEL, \
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.trigger_evt_src = EVT_SPI6_SPTI, \
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.irq_config = \
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{ \
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.irq = SPI6_TX_DMA_IRQn, \
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.irq_prio = SPI6_TX_DMA_INT_PRIO, \
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.int_src = SPI6_TX_DMA_INT_SRC, \
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} \
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}
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#endif /* SPI6_TX_DMA_CONFIG */
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#endif /* BSP_SPI6_TX_USING_DMA */
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#ifdef BSP_SPI6_RX_USING_DMA
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#ifndef SPI6_RX_DMA_CONFIG
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#define SPI6_RX_DMA_CONFIG \
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{ \
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.Instance = SPI6_RX_DMA_INSTANCE, \
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.channel = SPI6_RX_DMA_CHANNEL, \
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.trigger_evt_src = EVT_SPI6_SPRI, \
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.irq_config = \
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{ \
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.irq = SPI6_RX_DMA_IRQn, \
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.irq_prio = SPI6_RX_DMA_INT_PRIO, \
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.int_src = SPI6_RX_DMA_INT_SRC, \
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} \
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}
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#endif /* SPI6_RX_DMA_CONFIG */
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#endif /* BSP_SPI6_RX_USING_DMA */
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typedef struct __SPI_HandleType
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{
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M4_SPI_TypeDef *Instance; /* SPI registers base address */
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stc_spi_init_t Init; /* SPI communication parameters */
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}SPI_HandleType;
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struct hc32_hw_spi_cs
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{
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rt_uint8_t port;
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rt_uint16_t pin;
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};
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struct hc32_spi_config
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{
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M4_SPI_TypeDef *Instance;
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char *bus_name;
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struct dma_config *dma_rx;
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struct dma_config *dma_tx;
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};
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struct stm32_spi_device
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{
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rt_uint32_t pin;
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char *bus_name;
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char *device_name;
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};
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/* HC32 SPI index */
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struct spi_index
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{
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rt_uint32_t index;
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M4_SPI_TypeDef *Instance;
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};
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struct hc32_spi
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{
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struct rt_spi_bus spi_bus;
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SPI_HandleType handle;
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struct hc32_spi_config *config;
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struct rt_spi_configuration *cfg;
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rt_uint16_t spi_dma_flag;
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};
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/* HC32 SPI irq handler */
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struct spi_irq_handler
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{
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void (*rx_dma_irq_handler)(void);
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void (*tx_dma_irq_handler)(void);
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};
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rt_err_t hc32_hw_spi_device_attach(const char *bus_name,
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const char *device_name,
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uint8_t cs_gpio_port,
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uint16_t cs_gpio_pin);
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#ifdef __cplusplus
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}
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#endif
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#endif /* __DRV_SPI_H__ */
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