561 lines
45 KiB
C
561 lines
45 KiB
C
/*!
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\file gd32f3x0_rtc.h
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\brief definitions for the RTC
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\version 2017-06-06, V1.0.0, firmware for GD32F3x0
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\version 2019-06-01, V2.0.0, firmware for GD32F3x0
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*/
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/*
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Copyright (c) 2019, GigaDevice Semiconductor Inc.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice, this
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list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation
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and/or other materials provided with the distribution.
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3. Neither the name of the copyright holder nor the names of its contributors
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may be used to endorse or promote products derived from this software without
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specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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OF SUCH DAMAGE.
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*/
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#ifndef GD32F3X0_RTC_H
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#define GD32F3X0_RTC_H
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#include "gd32f3x0.h"
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/* RTC definitions */
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#define RTC RTC_BASE
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/* registers definitions */
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#define RTC_TIME REG32(RTC + 0x00000000U) /*!< RTC time of day register */
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#define RTC_DATE REG32(RTC + 0x00000004U) /*!< RTC date register */
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#define RTC_CTL REG32(RTC + 0x00000008U) /*!< RTC control register */
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#define RTC_STAT REG32(RTC + 0x0000000CU) /*!< RTC status register */
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#define RTC_PSC REG32(RTC + 0x00000010U) /*!< RTC time prescaler register */
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#define RTC_ALRM0TD REG32(RTC + 0x0000001CU) /*!< RTC alarm 0 time and date register */
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#define RTC_WPK REG32(RTC + 0x00000024U) /*!< RTC write protection key register */
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#define RTC_SS REG32(RTC + 0x00000028U) /*!< RTC sub second register */
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#define RTC_SHIFTCTL REG32(RTC + 0x0000002CU) /*!< RTC shift function control register */
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#define RTC_TTS REG32(RTC + 0x00000030U) /*!< RTC time of timestamp register */
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#define RTC_DTS REG32(RTC + 0x00000034U) /*!< RTC date of timestamp register */
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#define RTC_SSTS REG32(RTC + 0x00000038U) /*!< RTC sub second of timestamp register */
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#define RTC_HRFC REG32(RTC + 0x0000003CU) /*!< RTC high resolution frequency compensation registor */
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#define RTC_TAMP REG32(RTC + 0x00000040U) /*!< RTC tamper register */
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#define RTC_ALRM0SS REG32(RTC + 0x00000044U) /*!< RTC alarm 0 sub second register */
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#define RTC_BKP0 REG32(RTC + 0x00000050U) /*!< RTC backup 0 register */
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#define RTC_BKP1 REG32(RTC + 0x00000054U) /*!< RTC backup 1 register */
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#define RTC_BKP2 REG32(RTC + 0x00000058U) /*!< RTC backup 2 register */
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#define RTC_BKP3 REG32(RTC + 0x0000005CU) /*!< RTC backup 3 register */
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#define RTC_BKP4 REG32(RTC + 0x00000060U) /*!< RTC backup 4 register */
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/* bits definitions */
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/* RTC_TIME */
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#define RTC_TIME_SCU BITS(0,3) /*!< second units in BCD code */
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#define RTC_TIME_SCT BITS(4,6) /*!< second tens in BCD code */
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#define RTC_TIME_MNU BITS(8,11) /*!< minute units in BCD code */
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#define RTC_TIME_MNT BITS(12,14) /*!< minute tens in BCD code */
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#define RTC_TIME_HRU BITS(16,19) /*!< hour units in BCD code */
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#define RTC_TIME_HRT BITS(20,21) /*!< hour tens in BCD code */
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#define RTC_TIME_PM BIT(22) /*!< AM/PM notation */
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/* RTC_DATE */
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#define RTC_DATE_DAYU BITS(0,3) /*!< date units in BCD code */
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#define RTC_DATE_DAYT BITS(4,5) /*!< date tens in BCD code */
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#define RTC_DATE_MONU BITS(8,11) /*!< month units in BCD code */
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#define RTC_DATE_MONT BIT(12) /*!< month tens in BCD code */
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#define RTC_DATE_DOW BITS(13,15) /*!< day of week units */
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#define RTC_DATE_YRU BITS(16,19) /*!< year units in BCD code */
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#define RTC_DATE_YRT BITS(20,23) /*!< year tens in BCD code */
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/* RTC_CTL */
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#define RTC_CTL_TSEG BIT(3) /*!< valid event edge of time-stamp */
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#define RTC_CTL_REFEN BIT(4) /*!< reference clock detection function enable */
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#define RTC_CTL_BPSHAD BIT(5) /*!< shadow registers bypass control */
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#define RTC_CTL_CS BIT(6) /*!< display format of clock system */
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#define RTC_CTL_ALRM0EN BIT(8) /*!< alarm function enable */
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#define RTC_CTL_TSEN BIT(11) /*!< time-stamp function enable */
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#define RTC_CTL_ALRM0IE BIT(12) /*!< RTC alarm interrupt enable */
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#define RTC_CTL_TSIE BIT(15) /*!< time-stamp interrupt enable */
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#define RTC_CTL_A1H BIT(16) /*!< add 1 hour(summer time change) */
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#define RTC_CTL_S1H BIT(17) /*!< subtract 1 hour(winter time change) */
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#define RTC_CTL_DSM BIT(18) /*!< daylight saving mark */
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#define RTC_CTL_COS BIT(19) /*!< calibration output selection */
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#define RTC_CTL_OPOL BIT(20) /*!< output polarity */
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#define RTC_CTL_OS BITS(21,22) /*!< output selection */
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#define RTC_CTL_COEN BIT(23) /*!< calibration output enable */
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/* RTC_STAT */
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#define RTC_STAT_ALRM0WF BIT(0) /*!< alarm configuration can be write flag */
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#define RTC_STAT_SOPF BIT(3) /*!< shift function operation pending flag */
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#define RTC_STAT_YCM BIT(4) /*!< year configuration mark status flag */
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#define RTC_STAT_RSYNF BIT(5) /*!< register synchronization flag */
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#define RTC_STAT_INITF BIT(6) /*!< initialization state flag */
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#define RTC_STAT_INITM BIT(7) /*!< enter initialization mode */
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#define RTC_STAT_ALRM0F BIT(8) /*!< alarm occurs flag */
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#define RTC_STAT_TSF BIT(11) /*!< time-stamp flag */
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#define RTC_STAT_TSOVRF BIT(12) /*!< time-stamp overflow flag */
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#define RTC_STAT_TP0F BIT(13) /*!< RTC tamp 0 detected flag */
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#define RTC_STAT_TP1F BIT(14) /*!< RTC tamp 1 detected flag */
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#define RTC_STAT_SCPF BIT(16) /*!< recalibration pending flag */
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/* RTC_PSC */
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#define RTC_PSC_FACTOR_S BITS(0,14) /*!< synchronous prescaler factor */
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#define RTC_PSC_FACTOR_A BITS(16,22) /*!< asynchronous prescaler factor */
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/* RTC_ALRM0TD */
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#define RTC_ALRM0TD_SCU BITS(0,3) /*!< second units in BCD code */
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#define RTC_ALRM0TD_SCT BITS(4,6) /*!< second tens in BCD code */
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#define RTC_ALRM0TD_MSKS BIT(7) /*!< alarm second mask bit */
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#define RTC_ALRM0TD_MNU BITS(8,11) /*!< minutes units in BCD code */
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#define RTC_ALRM0TD_MNT BITS(12,14) /*!< minutes tens in BCD code */
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#define RTC_ALRM0TD_MSKM BIT(15) /*!< alarm minutes mask bit */
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#define RTC_ALRM0TD_HRU BITS(16,19) /*!< hour units in BCD code */
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#define RTC_ALRM0TD_HRT BITS(20,21) /*!< hour units in BCD code */
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#define RTC_ALRM0TD_PM BIT(22) /*!< AM/PM flag */
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#define RTC_ALRM0TD_MSKH BIT(23) /*!< alarm hour mask bit */
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#define RTC_ALRM0TD_DAYU BITS(24,27) /*!< date units or week day in BCD code */
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#define RTC_ALRM0TD_DAYT BITS(28,29) /*!< date tens in BCD code */
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#define RTC_ALRM0TD_DOWS BIT(30) /*!< day of week selection */
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#define RTC_ALRM0TD_MSKD BIT(31) /*!< alarm date mask bit */
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/* RTC_WPK */
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#define RTC_WPK_WPK BITS(0,7) /*!< key for write protection */
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/* RTC_SS */
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#define RTC_SS_SSC BITS(0,15) /*!< sub second value */
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/* RTC_SHIFTCTL */
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#define RTC_SHIFTCTL_SFS BITS(0,14) /*!< subtract a fraction of a second */
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#define RTC_SHIFTCTL_A1S BIT(31) /*!< one second add */
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/* RTC_TTS */
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#define RTC_TTS_SCU BITS(0,3) /*!< second units in BCD code */
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#define RTC_TTS_SCT BITS(4,6) /*!< second units in BCD code */
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#define RTC_TTS_MNU BITS(8,11) /*!< minute units in BCD code */
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#define RTC_TTS_MNT BITS(12,14) /*!< minute tens in BCD code */
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#define RTC_TTS_HRU BITS(16,19) /*!< hour units in BCD code */
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#define RTC_TTS_HRT BITS(20,21) /*!< hour tens in BCD code */
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#define RTC_TTS_PM BIT(22) /*!< AM/PM notation */
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/* RTC_DTS */
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#define RTC_DTS_DAYU BITS(0,3) /*!< date units in BCD code */
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#define RTC_DTS_DAYT BITS(4,5) /*!< date tens in BCD code */
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#define RTC_DTS_MONU BITS(8,11) /*!< month units in BCD code */
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#define RTC_DTS_MONT BIT(12) /*!< month tens in BCD code */
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#define RTC_DTS_DOW BITS(13,15) /*!< day of week units */
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/* RTC_SSTS */
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#define RTC_SSTS_SSC BITS(0,15) /*!< timestamp sub second units */
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/* RTC_HRFC */
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#define RTC_HRFC_CMSK BITS(0,8) /*!< calibration mask number */
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#define RTC_HRFC_CWND16 BIT(13) /*!< calibration window select 16 seconds */
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#define RTC_HRFC_CWND8 BIT(14) /*!< calibration window select 16 seconds */
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#define RTC_HRFC_FREQI BIT(15) /*!< increase RTC frequency by 488.5ppm */
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/* RTC_TAMP */
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#define RTC_TAMP_TP0EN BIT(0) /*!< tamper 0 detection enable */
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#define RTC_TAMP_TP0EG BIT(1) /*!< tamper 0 event trigger edge for RTC tamp 0 input */
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#define RTC_TAMP_TPIE BIT(2) /*!< tamper detection interrupt enable */
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#define RTC_TAMP_TP1EN BIT(3) /*!< tamper 1 detection enable */
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#define RTC_TAMP_TP1EG BIT(4) /*!< tamper 1 event trigger edge for RTC tamp 1 input */
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#define RTC_TAMP_TPTS BIT(7) /*!< make tamper function used for timestamp function */
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#define RTC_TAMP_FREQ BITS(8,10) /*!< sample frequency of tamper event detection */
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#define RTC_TAMP_FLT BITS(11,12) /*!< RTC tamp x filter count setting */
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#define RTC_TAMP_PRCH BITS(13,14) /*!< precharge duration time of RTC tamp x */
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#define RTC_TAMP_DISPU BIT(15) /*!< RTC tamp x pull up disable bit */
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#define RTC_TAMP_PC13VAL BIT(18) /*!< alarm output type control/PC13 output value */
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#define RTC_TAMP_PC13MDE BIT(19) /*!< PC13 mode */
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#define RTC_TAMP_PC14VAL BIT(20) /*!< PC14 output value */
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#define RTC_TAMP_PC14MDE BIT(21) /*!< PC14 mode */
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#define RTC_TAMP_PC15VAL BIT(22) /*!< PC15 output value */
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#define RTC_TAMP_PC15MDE BIT(23) /*!< PC15 mode */
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/* RTC_ALRM0SS */
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#define RTC_ALRM0SS_SSC BITS(0,14) /*!< alarm sub second value */
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#define RTC_ALRM0SS_MASKSSC BITS(24,27) /*!< mask control bit of SS */
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/* RTC_BKP0 */
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#define RTC_BKP0_DATA BITS(0,31) /*!< backup domain registers */
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/* RTC_BKP1 */
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#define RTC_BKP1_DATA BITS(0,31) /*!< backup domain registers */
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/* RTC_BKP2 */
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#define RTC_BKP2_DATA BITS(0,31) /*!< backup domain registers */
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/* RTC_BKP3 */
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#define RTC_BKP3_DATA BITS(0,31) /*!< backup domain registers */
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/* RTC_BKP4 */
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#define RTC_BKP4_DATA BITS(0,31) /*!< backup domain registers */
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/* constants definitions */
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/* structure for initialization of the RTC */
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typedef struct
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{
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uint8_t rtc_year; /*!< RTC year value: 0x0 - 0x99(BCD format) */
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uint8_t rtc_month; /*!< RTC month value */
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uint8_t rtc_date; /*!< RTC date value: 0x1 - 0x31(BCD format) */
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uint8_t rtc_day_of_week; /*!< RTC weekday value */
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uint8_t rtc_hour; /*!< RTC hour value */
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uint8_t rtc_minute; /*!< RTC minute value: 0x0 - 0x59(BCD format) */
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uint8_t rtc_second; /*!< RTC second value: 0x0 - 0x59(BCD format) */
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uint16_t rtc_factor_asyn; /*!< RTC asynchronous prescaler value: 0x0 - 0x7F */
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uint16_t rtc_factor_syn; /*!< RTC synchronous prescaler value: 0x0 - 0x7FFF */
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uint32_t rtc_am_pm; /*!< RTC AM/PM value */
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uint32_t rtc_display_format; /*!< RTC time notation */
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}rtc_parameter_struct;
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/* structure for RTC alarm configuration */
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typedef struct
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{
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uint32_t rtc_alarm_mask; /*!< RTC alarm mask */
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uint32_t rtc_weekday_or_date; /*!< specify RTC alarm is on date or weekday */
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uint8_t rtc_alarm_day; /*!< RTC alarm date or weekday value*/
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uint8_t rtc_alarm_hour; /*!< RTC alarm hour value */
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uint8_t rtc_alarm_minute; /*!< RTC alarm minute value: 0x0 - 0x59(BCD format) */
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uint8_t rtc_alarm_second; /*!< RTC alarm second value: 0x0 - 0x59(BCD format) */
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uint32_t rtc_am_pm; /*!< RTC alarm AM/PM value */
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}rtc_alarm_struct;
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/* structure for RTC time-stamp configuration */
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typedef struct
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{
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uint8_t rtc_timestamp_month; /*!< RTC time-stamp month value */
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uint8_t rtc_timestamp_date; /*!< RTC time-stamp date value: 0x1 - 0x31(BCD format) */
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uint8_t rtc_timestamp_day; /*!< RTC time-stamp weekday value */
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uint8_t rtc_timestamp_hour; /*!< RTC time-stamp hour value */
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uint8_t rtc_timestamp_minute; /*!< RTC time-stamp minute value: 0x0 - 0x59(BCD format) */
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uint8_t rtc_timestamp_second; /*!< RTC time-stamp second value: 0x0 - 0x59(BCD format) */
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uint32_t rtc_am_pm; /*!< RTC time-stamp AM/PM value */
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}rtc_timestamp_struct;
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/* structure for RTC tamper configuration */
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typedef struct
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{
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uint32_t rtc_tamper_source; /*!< RTC tamper source */
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uint32_t rtc_tamper_trigger; /*!< RTC tamper trigger */
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uint32_t rtc_tamper_filter; /*!< RTC tamper consecutive samples needed during a voltage level detection */
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uint32_t rtc_tamper_sample_frequency; /*!< RTC tamper sampling frequency during a voltage level detection */
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ControlStatus rtc_tamper_precharge_enable; /*!< RTC tamper precharge feature during a voltage level detection */
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uint32_t rtc_tamper_precharge_time; /*!< RTC tamper precharge duration if precharge feature is enabled */
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ControlStatus rtc_tamper_with_timestamp; /*!< RTC tamper time-stamp feature */
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}rtc_tamper_struct;
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/* time register value */
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#define TIME_SC(regval) (BITS(0,6) & ((uint32_t)(regval) << 0U)) /*!< write value to RTC_TIME_SC bit field */
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#define GET_TIME_SC(regval) GET_BITS((regval),0,6) /*!< get value of RTC_TIME_SC bit field */
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#define TIME_MN(regval) (BITS(8,14) & ((uint32_t)(regval) << 8U)) /*!< write value to RTC_TIME_MN bit field */
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#define GET_TIME_MN(regval) GET_BITS((regval),8,14) /*!< get value of RTC_TIME_MN bit field */
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#define TIME_HR(regval) (BITS(16,21) & ((uint32_t)(regval) << 16U)) /*!< write value to RTC_TIME_HR bit field */
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#define GET_TIME_HR(regval) GET_BITS((regval),16,21) /*!< get value of RTC_TIME_HR bit field */
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#define RTC_AM ((uint32_t)0x00000000U) /*!< AM format */
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#define RTC_PM RTC_TIME_PM /*!< PM format */
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/* date register value */
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#define DATE_DAY(regval) (BITS(0,5) & ((uint32_t)(regval) << 0U)) /*!< write value to RTC_DATE_DAY bit field */
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#define GET_DATE_DAY(regval) GET_BITS((regval),0,5) /*!< get value of RTC_DATE_DAY bit field */
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#define DATE_MON(regval) (BITS(8,12) & ((uint32_t)(regval) << 8U)) /*!< write value to RTC_DATE_MON bit field */
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#define GET_DATE_MON(regval) GET_BITS((regval),8,12) /*!< get value of RTC_DATE_MON bit field */
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#define RTC_JAN ((uint8_t)0x01U) /*!< Janurary */
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#define RTC_FEB ((uint8_t)0x02U) /*!< February */
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#define RTC_MAR ((uint8_t)0x03U) /*!< March */
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#define RTC_APR ((uint8_t)0x04U) /*!< April */
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#define RTC_MAY ((uint8_t)0x05U) /*!< May */
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#define RTC_JUN ((uint8_t)0x06U) /*!< June */
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#define RTC_JUL ((uint8_t)0x07U) /*!< July */
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#define RTC_AUG ((uint8_t)0x08U) /*!< August */
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#define RTC_SEP ((uint8_t)0x09U) /*!< September */
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#define RTC_OCT ((uint8_t)0x10U) /*!< October */
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#define RTC_NOV ((uint8_t)0x11U) /*!< November */
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#define RTC_DEC ((uint8_t)0x12U) /*!< December */
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#define DATE_DOW(regval) (BITS(13,15) & ((uint32_t)(regval) << 13U)) /*!< write value to RTC_DATE_DOW bit field */
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#define GET_DATE_DOW(regval) GET_BITS((regval),13,15) /*!< get value of RTC_DATE_DOW bit field */
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#define RTC_MONDAY ((uint8_t)0x01U) /*!< Monday */
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#define RTC_TUESDAY ((uint8_t)0x02U) /*!< Tuesday */
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#define RTC_WEDSDAY ((uint8_t)0x03U) /*!< Wednesday */
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#define RTC_THURSDAY ((uint8_t)0x04U) /*!< Thursday */
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#define RTC_FRIDAY ((uint8_t)0x05U) /*!< Friday */
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#define RTC_SATURDAY ((uint8_t)0x06U) /*!< Saturday */
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#define RTC_SUNDAY ((uint8_t)0x07U) /*!< Sunday */
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#define DATE_YR(regval) (BITS(16,23) & ((uint32_t)(regval) << 16U)) /*!< write value to RTC_DATE_YR bit field */
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#define GET_DATE_YR(regval) GET_BITS((regval),16,23) /*!< get value of RTC_DATE_YR bit field */
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/* ctl register value */
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#define CTL_OS(regval) (BITS(21,22) & ((uint32_t)(regval) << 21U)) /*!< write value to RTC_CTL_OS bit field */
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#define RTC_OS_DISABLE CTL_OS(0) /*!< disable output RTC_ALARM */
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#define RTC_OS_ENABLE CTL_OS(1) /*!< enable alarm flag output */
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#define RTC_CALIBRATION_512HZ RTC_CTL_COEN /*!< calibration output of 512Hz is enable */
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#define RTC_CALIBRATION_1HZ RTC_CTL_COEN | RTC_CTL_COS /*!< calibration output of 1Hz is enable */
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#define RTC_ALARM_HIGH RTC_CTL_OS_ENABLE /*!< enable alarm flag output with high level */
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#define RTC_ALARM_LOW RTC_CTL_OS_ENABLE | RTC_CTL_OPOL /*!< enable alarm flag output with low level*/
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#define RTC_24HOUR ((uint32_t)0x00000000U) /*!< 24-hour format */
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#define RTC_12HOUR RTC_CTL_CS /*!< 12-hour format */
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#define RTC_TIMESTAMP_RISING_EDGE ((uint32_t)0x00000000U) /*!< rising edge is valid event edge for time-stamp event */
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#define RTC_TIMESTAMP_FALLING_EDGE RTC_CTL_TSEG /*!< falling edge is valid event edge for time-stamp event */
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/* psc register value */
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#define PSC_FACTOR_S(regval) (BITS(0,14) & ((uint32_t)(regval) << 0U)) /*!< write value to RTC_PSC_FACTOR_S bit field */
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#define GET_PSC_FACTOR_S(regval) GET_BITS((regval),0,14) /*!< get value of RTC_PSC_FACTOR_S bit field */
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#define PSC_FACTOR_A(regval) (BITS(16,22) & ((uint32_t)(regval) << 16U)) /*!< write value to RTC_PSC_FACTOR_A bit field */
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#define GET_PSC_FACTOR_A(regval) GET_BITS((regval),16,22) /*!< get value of RTC_PSC_FACTOR_A bit field */
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/* alrm0td register value */
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#define ALRM0TD_SC(regval) (BITS(0,6) & ((uint32_t)(regval)<< 0U)) /*!< write value to RTC_ALRM0TD_SC bit field */
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#define GET_ALRM0TD_SC(regval) GET_BITS((regval),0,6) /*!< get value of RTC_ALRM0TD_SC bit field */
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#define ALRM0TD_MN(regval) (BITS(8,14) & ((uint32_t)(regval) << 8U)) /*!< write value to RTC_ALRM0TD_MN bit field */
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#define GET_ALRM0TD_MN(regval) GET_BITS((regval),8,14) /*!< get value of RTC_ALRM0TD_MN bit field */
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#define ALRM0TD_HR(regval) (BITS(16,21) & ((uint32_t)(regval) << 16U)) /*!< write value to RTC_ALRM0TD_HR bit field */
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#define GET_ALRM0TD_HR(regval) GET_BITS((regval),16,21) /*!< get value of RTC_ALRM0TD_HR bit field */
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#define ALRM0TD_DAY(regval) (BITS(24,29) & ((uint32_t)(regval) << 24U)) /*!< write value to RTC_ALRM0TD_DAY bit field */
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#define GET_ALRM0TD_DAY(regval) GET_BITS((regval),24,29) /*!< get value of RTC_ALRM0TD_DAY bit field */
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#define RTC_ALARM_NONE_MASK ((uint32_t)0x00000000U) /*!< alarm none mask */
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#define RTC_ALARM_DATE_MASK RTC_ALRM0TD_MSKD /*!< alarm date mask */
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#define RTC_ALARM_HOUR_MASK RTC_ALRM0TD_MSKH /*!< alarm hour mask */
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#define RTC_ALARM_MINUTE_MASK RTC_ALRM0TD_MSKM /*!< alarm minute mask */
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#define RTC_ALARM_SECOND_MASK RTC_ALRM0TD_MSKS /*!< alarm second mask */
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#define RTC_ALARM_ALL_MASK (RTC_ALRM0TD_MSKD|RTC_ALRM0TD_MSKH|RTC_ALRM0TD_MSKM|RTC_ALRM0TD_MSKS) /*!< alarm all mask */
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#define RTC_ALARM_DATE_SELECTED ((uint32_t)0x00000000U) /*!< alarm date format selected */
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#define RTC_ALARM_WEEKDAY_SELECTED RTC_ALRM0TD_DOWS /*!< alarm weekday format selected */
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/* wpk register value */
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#define WPK_WPK(regval) (BITS(0,7) & ((uint32_t)(regval) << 0U)) /*!< write value to RTC_WPK_WPK bit field */
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/* ss register value */
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#define SS_SSC(regval) (BITS(0,15) & ((uint32_t)(regval) << 0U)) /*!< write value to RTC_SS_SSC bit field */
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/* shiftctl register value */
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#define SHIFTCTL_SFS(regval) (BITS(0,14) & ((uint32_t)(regval) << 0U)) /*!< write value to RTC_SHIFTCTL_SFS bit field */
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#define RTC_SHIFT_ADD1S_RESET ((uint32_t)0x00000000U) /*!< not add 1 second */
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#define RTC_SHIFT_ADD1S_SET RTC_SHIFTCTL_A1S /*!< add one second to the clock */
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/* tts register value */
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#define TTS_SC(regval) (BITS(0,6) & ((uint32_t)(regval) << 0U)) /*!< write value to RTC_TTS_SC bit field */
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#define GET_TTS_SC(regval) GET_BITS((regval),0,6) /*!< get value of RTC_TTS_SC bit field */
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#define TTS_MN(regval) (BITS(8,14) & ((uint32_t)(regval) << 8U)) /*!< write value to RTC_TTS_MN bit field */
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#define GET_TTS_MN(regval) GET_BITS((regval),8,14) /*!< get value of RTC_TTS_MN bit field */
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#define TTS_HR(regval) (BITS(16,21) & ((uint32_t)(regval) << 16U)) /*!< write value to RTC_TTS_HR bit field */
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#define GET_TTS_HR(regval) GET_BITS((regval),16,21) /*!< get value of RTC_TTS_HR bit field */
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/* dts register value */
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#define DTS_DAY(regval) (BITS(0,5) & ((uint32_t)(regval) << 0U)) /*!< write value to RTC_DTS_DAY bit field */
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#define GET_DTS_DAY(regval) GET_BITS((regval),0,5) /*!< get value of RTC_DTS_DAY bit field */
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#define DTS_MON(regval) (BITS(8,12) & ((uint32_t)(regval) << 8U)) /*!< write value to RTC_DTS_MON bit field */
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#define GET_DTS_MON(regval) GET_BITS((regval),8,12) /*!< get value of RTC_DTS_MON bit field */
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#define DTS_DOW(regval) (BITS(13,15) & ((uint32_t)(regval) << 13U)) /*!< write value to RTC_DTS_DOW bit field */
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#define GET_DTS_DOW(regval) GET_BITS((regval),13,15) /*!< get value of RTC_DTS_DOW bit field */
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/* ssts register value */
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#define SSTS_SSC(regval) (BITS(0,15) & ((uint32_t)(regval) << 0U)) /*!< write value to RTC_SSTS_SSC bit field */
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/* hrfc register value */
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#define HRFC_CMSK(regval) (BITS(0,8) & ((uint32_t)(regval) << 0U)) /*!< write value to RTC_HRFC_CMSK bit field */
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#define RTC_CALIBRATION_WINDOW_32S ((uint32_t)0x00000000U) /*!< 2exp20 RTCCLK cycles, 32s if RTCCLK = 32768 Hz */
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#define RTC_CALIBRATION_WINDOW_16S RTC_HRFC_CWND16 /*!< 2exp19 RTCCLK cycles, 16s if RTCCLK = 32768 Hz */
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#define RTC_CALIBRATION_WINDOW_8S RTC_HRFC_CWND8 /*!< 2exp18 RTCCLK cycles, 8s if RTCCLK = 32768 Hz */
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#define RTC_CALIBRATION_PLUS_SET RTC_HRFC_FREQI /*!< increase RTC frequency by 488.5ppm */
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#define RTC_CALIBRATION_PLUS_RESET ((uint32_t)0x00000000U) /*!< no effect */
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/* tamp register value */
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#define TAMP_FREQ(regval) (BITS(8,10) & ((uint32_t)(regval) << 8U)) /*!< write value to RTC_TAMP_FREQ bit field */
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#define RTC_FREQ_DIV32768 TAMP_FREQ(0) /*!< sample once every 32768 RTCCLK(1Hz if RTCCLK=32.768KHz) */
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#define RTC_FREQ_DIV16384 TAMP_FREQ(1) /*!< sample once every 16384 RTCCLK(2Hz if RTCCLK=32.768KHz) */
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#define RTC_FREQ_DIV8192 TAMP_FREQ(2) /*!< sample once every 8192 RTCCLK(4Hz if RTCCLK=32.768KHz) */
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#define RTC_FREQ_DIV4096 TAMP_FREQ(3) /*!< sample once every 4096 RTCCLK(8Hz if RTCCLK=32.768KHz) */
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#define RTC_FREQ_DIV2048 TAMP_FREQ(4) /*!< sample once every 2048 RTCCLK(16Hz if RTCCLK=32.768KHz) */
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#define RTC_FREQ_DIV1024 TAMP_FREQ(5) /*!< sample once every 1024 RTCCLK(32Hz if RTCCLK=32.768KHz) */
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#define RTC_FREQ_DIV512 TAMP_FREQ(6) /*!< sample once every 512 RTCCLK(64Hz if RTCCLK=32.768KHz) */
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#define RTC_FREQ_DIV256 TAMP_FREQ(7) /*!< sample once every 256 RTCCLK(128Hz if RTCCLK=32.768KHz) */
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#define TAMP_FLT(regval) (BITS(11,12) & ((uint32_t)(regval) << 11U)) /*!< write value to RTC_TAMP_FLT bit field */
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#define RTC_FLT_EDGE TAMP_FLT(0) /*!< detecting tamper event using edge mode. precharge duration is disabled automatically */
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#define RTC_FLT_2S TAMP_FLT(1) /*!< detecting tamper event using level mode.2 consecutive valid level samples will make a effective tamper event */
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#define RTC_FLT_4S TAMP_FLT(2) /*!< detecting tamper event using level mode.4 consecutive valid level samples will make an effective tamper event */
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#define RTC_FLT_8S TAMP_FLT(3) /*!< detecting tamper event using level mode.8 consecutive valid level samples will make a effective tamper event */
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#define TAMP_PRCH(regval) (BITS(13,14) & ((uint32_t)(regval) << 13U)) /*!< write value to RTC_TAMP_PRCH bit field */
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#define RTC_PRCH_1C TAMP_PRCH(0) /*!< 1 RTC clock prechagre time before each sampling */
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#define RTC_PRCH_2C TAMP_PRCH(1) /*!< 2 RTC clock prechagre time before each sampling */
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#define RTC_PRCH_4C TAMP_PRCH(2) /*!< 4 RTC clock prechagre time before each sampling */
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#define RTC_PRCH_8C TAMP_PRCH(3) /*!< 8 RTC clock prechagre time before each sampling */
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#define RTC_TAMPER0 RTC_TAMP_TP0EN /*!< tamper 0 detection enable */
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#define RTC_TAMPER1 RTC_TAMP_TP1EN /*!< tamper 1 detection enable */
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#define RTC_TAMPER_TRIGGER_EDGE_RISING ((uint32_t)0x00000000U) /*!< tamper detection is in rising edge mode */
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#define RTC_TAMPER_TRIGGER_EDGE_FALLING RTC_TAMP_TP0EG /*!< tamper detection is in falling edge mode */
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#define RTC_TAMPER_TRIGGER_LEVEL_LOW ((uint32_t)0x00000000U) /*!< tamper detection is in low level mode */
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#define RTC_TAMPER_TRIGGER_LEVEL_HIGH RTC_TAMP_TP0EG /*!< tamper detection is in high level mode */
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#define RTC_TAMPER_TRIGGER_POS ((uint32_t)0x00000001U) /* shift position of trigger relative to source */
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#define RTC_ALARM_OUTPUT_OD ((uint32_t)0x00000000U) /*!< RTC alarm output open-drain mode */
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#define RTC_ALARM_OUTPUT_PP RTC_TAMP_PC13VAL /*!< RTC alarm output push-pull mode */
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/* alrm0ss register value */
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#define ALRM0SS_SSC(regval) (BITS(0,14) & ((uint32_t)(regval)<< 0U)) /*!< write value to RTC_ALRM0SS_SSC bit field */
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#define ALRM0SS_MASKSSC(regval) (BITS(24,27) & ((uint32_t)(regval) << 24U)) /*!< write value to RTC_ALRM0SS_MASKSSC bit field */
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#define RTC_MASKSSC_0_14 ALRM0SS_MASKSSC(0) /*!< mask alarm subsecond configuration */
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#define RTC_MASKSSC_1_14 ALRM0SS_MASKSSC(1) /*!< mask RTC_ALRM0SS_SSC[14:1], and RTC_ALRM0SS_SSC[0] is to be compared */
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#define RTC_MASKSSC_2_14 ALRM0SS_MASKSSC(2) /*!< mask RTC_ALRM0SS_SSC[14:2], and RTC_ALRM0SS_SSC[1:0] is to be compared */
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#define RTC_MASKSSC_3_14 ALRM0SS_MASKSSC(3) /*!< mask RTC_ALRM0SS_SSC[14:3], and RTC_ALRM0SS_SSC[2:0] is to be compared */
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#define RTC_MASKSSC_4_14 ALRM0SS_MASKSSC(4) /*!< mask RTC_ALRM0SS_SSC[14:4], and RTC_ALRM0SS_SSC[3:0] is to be compared */
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#define RTC_MASKSSC_5_14 ALRM0SS_MASKSSC(5) /*!< mask RTC_ALRM0SS_SSC[14:5], and RTC_ALRM0SS_SSC[4:0] is to be compared */
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#define RTC_MASKSSC_6_14 ALRM0SS_MASKSSC(6) /*!< mask RTC_ALRM0SS_SSC[14:6], and RTC_ALRM0SS_SSC[5:0] is to be compared */
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#define RTC_MASKSSC_7_14 ALRM0SS_MASKSSC(7) /*!< mask RTC_ALRM0SS_SSC[14:7], and RTC_ALRM0SS_SSC[6:0] is to be compared */
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#define RTC_MASKSSC_8_14 ALRM0SS_MASKSSC(8) /*!< mask RTC_ALRM0SS_SSC[14:8], and RTC_ALRM0SS_SSC[7:0] is to be compared */
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#define RTC_MASKSSC_9_14 ALRM0SS_MASKSSC(9) /*!< mask RTC_ALRM0SS_SSC[14:9], and RTC_ALRM0SS_SSC[8:0] is to be compared */
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#define RTC_MASKSSC_10_14 ALRM0SS_MASKSSC(10) /*!< mask RTC_ALRM0SS_SSC[14:10], and RTC_ALRM0SS_SSC[9:0] is to be compared */
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#define RTC_MASKSSC_11_14 ALRM0SS_MASKSSC(11) /*!< mask RTC_ALRM0SS_SSC[14:11], and RTC_ALRM0SS_SSC[10:0] is to be compared */
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#define RTC_MASKSSC_12_14 ALRM0SS_MASKSSC(12) /*!< mask RTC_ALRM0SS_SSC[14:12], and RTC_ALRM0SS_SSC[11:0] is to be compared */
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#define RTC_MASKSSC_13_14 ALRM0SS_MASKSSC(13) /*!< mask RTC_ALRM0SS_SSC[14:13], and RTC_ALRM0SS_SSC[12:0] is to be compared */
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#define RTC_MASKSSC_14 ALRM0SS_MASKSSC(14) /*!< mask RTC_ALRM0SS_SSC[14], and RTC_ALRM0SS_SSC[13:0] is to be compared */
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#define RTC_MASKSSC_NONE ALRM0SS_MASKSSC(15) /*!< mask none, and RTC_ALRM0SS_SSC[14:0] is to be compared */
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/* RTC interrupt source */
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#define RTC_INT_TIMESTAMP RTC_CTL_TSIE /*!< time-stamp interrupt enable */
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#define RTC_INT_ALARM RTC_CTL_ALRM0IE /*!< RTC alarm interrupt enable */
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#define RTC_INT_TAMP RTC_TAMP_TPIE /*!< tamper detection interrupt enable */
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/* write protect key */
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#define RTC_UNLOCK_KEY1 ((uint8_t)0xCAU) /*!< RTC unlock key1 */
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#define RTC_UNLOCK_KEY2 ((uint8_t)0x53U) /*!< RTC unlock key2 */
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#define RTC_LOCK_KEY ((uint8_t)0xFFU) /*!< RTC lock key */
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/* registers reset value */
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#define RTC_REGISTER_RESET ((uint32_t)0x00000000U) /*!< RTC common register reset value */
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#define RTC_DATE_RESET ((uint32_t)0x00002101U) /*!< RTC_DATE register reset value */
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#define RTC_STAT_RESET ((uint32_t)0x00000007U) /*!< RTC_STAT register reset value */
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#define RTC_PSC_RESET ((uint32_t)0x007F00FFU) /*!< RTC_PSC register reset value */
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/* RTC timeout value */
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#define RTC_INITM_TIMEOUT ((uint32_t)0x00004000U) /*!< initialization state flag timeout */
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#define RTC_RSYNF_TIMEOUT ((uint32_t)0x00008000U) /*!< register synchronization flag timeout */
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#define RTC_HRFC_TIMEOUT ((uint32_t)0x00001000U) /*!< recalibration pending flag timeout */
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#define RTC_SHIFTCTL_TIMEOUT ((uint32_t)0x00001000U) /*!< shift function operation pending flag timeout */
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#define RTC_ALRM0WF_TIMEOUT ((uint32_t)0x00008000U) /*!< alarm configuration can be write flag timeout */
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/* RTC flag */
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#define RTC_FLAG_RECALIBRATION RTC_STAT_SCPF /*!< recalibration pending flag */
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#define RTC_FLAG_TAMP1 RTC_STAT_TP1F /*!< tamper 1 event flag */
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#define RTC_FLAG_TAMP0 RTC_STAT_TP0F /*!< tamper 0 event flag */
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#define RTC_FLAG_TIMESTAMP_OVERFLOW RTC_STAT_TSOVRF /*!< time-stamp overflow event flag */
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#define RTC_FLAG_TIMESTAMP RTC_STAT_TSF /*!< time-stamp event flag */
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#define RTC_FLAG_ALARM0 RTC_STAT_ALRM0F /*!< alarm event flag */
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#define RTC_FLAG_INIT RTC_STAT_INITF /*!< init mode event flag */
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#define RTC_FLAG_RSYN RTC_STAT_RSYNF /*!< registers synchronized flag */
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#define RTC_FLAG_YCM RTC_STAT_YCM /*!< year parameter configured event flag */
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#define RTC_FLAG_SHIFT RTC_STAT_SOPF /*!< shift operation pending flag */
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#define RTC_FLAG_ALARM0_WRITTEN RTC_STAT_ALRM0WF /*!< alarm written available flag */
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/* function declarations */
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/* reset most of the RTC registers */
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ErrStatus rtc_deinit(void);
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/* initialize RTC registers */
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ErrStatus rtc_init(rtc_parameter_struct* rtc_initpara_struct);
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/* enter RTC init mode */
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ErrStatus rtc_init_mode_enter(void);
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/* exit RTC init mode */
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void rtc_init_mode_exit(void);
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/* wait until RTC_TIME and RTC_DATE registers are synchronized with APB clock, and the shadow registers are updated */
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ErrStatus rtc_register_sync_wait(void);
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/* get current time and date */
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void rtc_current_time_get(rtc_parameter_struct* rtc_initpara_struct);
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/* get current subsecond value */
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uint32_t rtc_subsecond_get(void);
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/* configure RTC alarm */
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void rtc_alarm_config(rtc_alarm_struct* rtc_alarm_time);
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/* configure subsecond of RTC alarm */
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void rtc_alarm_subsecond_config(uint32_t mask_subsecond, uint32_t subsecond);
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/* get RTC alarm */
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void rtc_alarm_get(rtc_alarm_struct* rtc_alarm_time);
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/* get RTC alarm subsecond */
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uint32_t rtc_alarm_subsecond_get(void);
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/* enable RTC alarm */
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void rtc_alarm_enable(void);
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/* disable RTC alarm */
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ErrStatus rtc_alarm_disable(void);
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/* enable RTC time-stamp */
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void rtc_timestamp_enable(uint32_t edge);
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/* disable RTC time-stamp */
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void rtc_timestamp_disable(void);
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/* get RTC timestamp time and date */
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void rtc_timestamp_get(rtc_timestamp_struct* rtc_timestamp);
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/* get RTC time-stamp subsecond */
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uint32_t rtc_timestamp_subsecond_get(void);
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/* enable RTC tamper */
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void rtc_tamper_enable(rtc_tamper_struct* rtc_tamper);
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/* disable RTC tamper */
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void rtc_tamper_disable(uint32_t source);
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/* enable specified RTC interrupt */
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void rtc_interrupt_enable(uint32_t interrupt);
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/* disble specified RTC interrupt */
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void rtc_interrupt_disable(uint32_t interrupt);
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/* check specified flag */
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FlagStatus rtc_flag_get(uint32_t flag);
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/* clear specified flag */
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void rtc_flag_clear(uint32_t flag);
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/* configure RTC alternate output source */
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void rtc_alter_output_config(uint32_t source, uint32_t mode);
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/* configure RTC calibration register */
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ErrStatus rtc_calibration_config(uint32_t window, uint32_t plus, uint32_t minus);
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/* ajust the daylight saving time by adding or substracting one hour from the current time */
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void rtc_hour_adjust(uint32_t operation);
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/* ajust RTC second or subsecond value of current time */
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ErrStatus rtc_second_adjust(uint32_t add, uint32_t minus);
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/* enable RTC bypass shadow registers function */
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void rtc_bypass_shadow_enable(void);
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/* disable RTC bypass shadow registers function */
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void rtc_bypass_shadow_disable(void);
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/* enable RTC reference clock detection function */
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ErrStatus rtc_refclock_detection_enable(void);
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/* disable RTC reference clock detection function */
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ErrStatus rtc_refclock_detection_disable(void);
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#endif /* GD32F3X0_RTC_H */
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